SRAM cell and SRAM device

1. A static random access memory (SRAM) cell including a first, a second, a third and a fourth semiconductor thin plate that are provided on a single substrate and are arranged in parallel to each other in order, on the first semiconductor thin plate being formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, on the second semiconductor thin plate being formed a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, on the third semiconductor thin plate being formed a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, on the fourth semiconductor thin plate being formed a sixth four-terminal double-gate FET with the first conductivity type,

wherein the third and the fourth four-terminal double-gate FETs form select transistors with their logic signal input gates of the third and the fourth four-terminal double-gate FETs being connected to the word line,

wherein the first and the second four-terminal double-gate FETs, and the fifth and the sixth four-terminal double-gate FETs form cross-coupled complementary metal-oxide-semiconductor (CMOS) inverters to form a flip-flop, and wherein

logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on sides facing the second and the third semiconductor thin plates, respectively,

threshold voltage control gates of the second and the third four-terminal double-gate FETs and the threshold voltage control gates of the fourth and the fifth four-terminal double-gate FETs are arranged on sides facing each other and each of the respective threshold voltage control gates of the second to the fifth four-terminal double-gate FETs is commonly connected to a first bias line,

threshold voltage control gates of the first and the sixth four-terminal double-gate FETs are commonly connected to a second bias line, and

a word line, the first bias line and the second bias line are arranged orthogonally to a direction of arrangement of the first to the fourth semiconductor thin plates.

2. A static random access memory (SRAM) cell including a first, a second, a third and a fourth semiconductor thin plate that are provided on a single substrate and are arranged in parallel to each other in order, on the first semiconductor thin plate being formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, on the second semiconductor thin plate being formed a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, on the third semiconductor thin plate being formed a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, on the fourth semiconductor thin plate being formed a sixth four-terminal double-gate FET with the first conductivity type,

wherein the third and the fourth four-terminal double-gate FETs form select transistors with logic signal input gates of the third and the fourth four-terminal double-gate FETs being connected to the word line,

wherein the first and the second four-terminal double-gate FETs, and the fifth and the sixth four-terminal double-gate FETs form cross-coupled inverters to form a flip-flop, and wherein

logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on sides facing the second and the third semiconductor thin plates, respectively,

threshold voltage control gates of the second and the fifth four-terminal double-gate FETs are commonly connected to a first bias line, and threshold voltage control gates of the third and the fourth four-terminal double-gate FETs are commonly connected to a third bias line,

threshold voltage control gates of the first and the sixth four-terminal double-gate FETs are commonly connected to a second bias line, and

a word line, the first bias line, the second bias line and the third bias line are arranged orthogonally to a direction of arrangement of the first to the fourth semiconductor thin plates.

3. The SRAM cell in accordance with claim 1 or 2 , wherein logic signal input gates of the first and the second four-terminal double-gate FETs are arranged in a position facing each other and logic signal input gates of the fifth and the sixth four-terminal double-gate FETs are arranged in a position facing each other.

4. The SRAM cell in accordance with any one of claims 1 and 2 , wherein the third and the fourth four-terminal double-gate FETs are arranged adjacent to each other.

5. The SRAM cell in accordance with any one of claims 1 and 2 , wherein the first and the sixth four-terminal double-gate FETs are formed with channel widths different from channel widths of the second to the fifth four-terminal double-gate FETs.

6. An SRAM device, wherein a plurality of SRAM cells, each in accordance with the SRAM cell of any one of claims 1 and 2 , are arranged in a direction of arrangement of the first to the fourth semiconductor thin plates with line symmetry.

7. The SRAM device in accordance with claim 6 , wherein the second and the third semiconductor thin plates, each having the second conductivity type, are formed as a semiconductor thin plate commonly used for the arrangement of the plurality of SRAM cells.