Counter circuit, latency counter, semiconductor memory device including the same, and data processing system

1. A counter circuit comprising:

a frequency dividing circuit that generates a plurality of frequency dividing clocks based on a clock signal, the frequency dividing clocks including at least first and second frequency dividing clocks, which differ in phase to each other;

a first counter that counts the first frequency dividing clock;

a second counter that fetches a count value of the first counter in synchronism with the second frequency dividing clock; and

a selection circuit that exclusively selects count values of the first and second counters.

2. The counter circuit as claimed in claim 1 , wherein the selection circuit selects a count value of the first counter based on the first frequency dividing clock, and the selection circuit selects a count value of the second counter based on the second frequency dividing clock.

3. The counter circuit as claimed in claim 1 , wherein the first counter includes a ripple counter that outputs the count value in a binary format.

4. The counter circuit as claimed in claim 3 , wherein the first counter further includes a first delay circuit that matches change timings of a plurality of bits configuring the count value.

5. The counter circuit as claimed in claim 4 , wherein the second counter includes a second delay circuit that delays the second frequency dividing clock, and the second counter fetches the count value of the first counter in response to the second frequency dividing clock delayed by the second delay circuit.

6. The counter circuit as claimed in claim 5 , wherein a delay amount of the second delay circuit is larger than a delay amount of the first delay circuit.

7. A latency counter that counts a latency of an internal command in synchronism with a clock signal, the latency counter comprising:

a counter circuit; and

a point-shift FIFO circuit including a plurality of latch circuits, wherein

the counter circuit includes:

a frequency dividing circuit that generates a plurality of frequency dividing clocks based on a clock signal, the frequency dividing clocks including at least first and second frequency dividing clocks, which differ in phase to each other;

a first counter that counts the first frequency dividing clock;

a second counter that fetches a count value of the first counter in synchronism with the second frequency dividing clock; and

a selection circuit that exclusively selects count values of the first and second counters,

the point-shift FIFO circuit fetches the internal command to any one of the latch circuits based on a count value of the counter circuit, and outputs the internal command fetched to any one of the latch circuits based on a count value of the counter circuit.

8. The latency counter as claimed in claim 7 , wherein the point-shift FIFO circuit includes:

an input selection circuit that supplies the internal command to any one of a plurality of signal paths based on the count value of the counter circuit;

a shift circuit that supplies the internal command to a predetermined latch circuit based on a predetermined relationship between the signal paths and the latch circuits; and

an output selection circuit that outputs the internal command fetched to any one of the latch circuits based on the count value of the counter circuit.

9. The latency counter as claimed in claim 8 , wherein each of the latch circuits includes an SR (set/reset) latch circuit that is set in response to input of the internal command and that is reset in response to output of the internal command.

10. The latency counter as claimed in claim 8 , wherein the shift circuit is capable of changing the relationship between the signal paths and the latch circuits based on a setting signal.

11. The latency counter as claimed in claim 7 , wherein the point-shift FIFO circuit includes:

a first wired-OR circuit that logically operates based on outputs of a plurality of latch circuits belonging to a first group among the latch circuits;

a second wired-OR circuit that logically operates based on outputs of a plurality of latch circuits belonging to a second group among the latch circuits;

a gate circuit that logically operates based on outputs of at least the first and second wired-OR circuits; and

first and second reset circuits that reset the first and second wired-OR circuits, respectively, based on the count value of the counter circuit.

12. The latency counter as claimed in claim 11 , wherein

the first reset circuit resets the first wired-OR circuit in response to the count value of the counter circuit indicating a predetermined latch circuit different from the latch circuits belonging to the first group, and

the second reset circuit resets the second wired-OR circuit in response to the count value of the counter circuit indicating a predetermined latch circuit different from the latch circuits belonging to the second group.

13. The latency counter as claimed in claim 7 , further comprising a mode switching circuit that relatively promptly supplies the internal command to the point-shift FIFO circuit in a first operation mode, and relatively slowly supplies the internal command to the point-shift FIFO circuit in a second operation mode.

14. The latency counter as claimed in claim 13 , wherein the first operation mode is a state where the clock signal is phase-controlled, and the second operation mode is a state where the clock signal is not phase-controlled.

15. A semiconductor memory device comprising a latency counter that counts a latency of an internal command in synchronism with a clock signal, the latency counter including a counter circuit and a point-shift FIFO circuit having a plurality of latch circuits, wherein

the counter circuit includes:

a frequency dividing circuit that generates a plurality of frequency dividing clocks based on a clock signal, the frequency dividing clocks including at least first and second frequency dividing clocks, which differ in phase to each other;

a first counter that counts the first frequency dividing clock;

a second counter that fetches a count value of the first counter in synchronism with the second frequency dividing clock; and

a selection circuit that exclusively selects count values of the first and second counters,

the point-shift FIFO circuit fetches the internal command to any one of the latch circuits based on a count value of the counter circuit, and outputs the internal command fetched to any one of the latch circuits based on a count value of the counter circuit.

16. A data processing system comprising a semiconductor memory device and a data processor connected to each other by a system bus, the semiconductor memory device including a latency counter that counts a latency of an internal command in synchronism with a clock signal, the latency counter including a counter circuit and a point-shift FIFO circuit having a plurality of latch circuits, wherein

the counter circuit includes:

a frequency dividing circuit that generates a plurality of frequency dividing clocks based on a clock signal, the frequency dividing clocks including at least first and second frequency dividing clocks, which differ in phase to each other;

a first counter that counts the first frequency dividing clock;

a second counter that fetches a count value of the first counter in synchronism with the second frequency dividing clock; and

a selection circuit that exclusively selects count values of the first and second counters,

the point-shift FIFO circuit fetches the internal command to any one of the latch circuits based on a count value of the counter circuit, and outputs the internal command fetched to any one of the latch circuits based on a count value of the counter circuit.