Bus relay device and bus control system including bus masters, interconnect section, and bridge section
A combination includes a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus, a second bus master coupled to the first bus to output a second signal group including at least one of signals onto the first bus, an interconnect section coupled between the first bus and a second bus to receive the first and second signal groups and to output a third signal group including at least one of signals onto the second bus, and a bridge section coupled between the second bus and a third bus to receive the third signal group and to output a fourth signal group including at least one of signals onto the third bus free from performing a selecting operation for the third signal group.
1. A bus apparatus, comprising:
a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus;
a second bus master coupled to the first bus to output a second signal group including at least one of signals onto the first bus;
an interconnect section coupled between the first bus and a second bus to receive the first and second signal groups and to output a third signal group including at least one of signals onto the second bus; and
a bridge section coupled between the second bus and a third bus to receive the third signal group and to output a fourth signal group including at least one of signals onto the third bus free from performing a selecting operation for the third signal group,
wherein a bit width of the third signal group indicating an address is equal to a bit width of the first signal group indicating an address.
2. The bus apparatus according to claim 1 , further comprising:
a bus slave coupled to the third bus to receive the fourth signal group.
3. The bus apparatus according to claim 1 , wherein the bit width of the third signal group is equal to a bit width of the second signal group indicating an address.
4. The bus apparatus according to claim 1 , wherein the bit width of the third signal group indicating an address is wider than a bit width of the fourth signal group indicating an address.
5. A bus system, comprising:
a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus;
a second bus master coupled to the first bus to output a second signal group including at least one of signals onto the first bus;
an interconnect section coupled between the first bus and a second bus to receive the first and second signal groups and to output a third signal group including at least one of signals onto the second bus; and
a bridge section coupled between the second bus and a third bus to receive the third signal group and to output a fourth signal group including at least one of signals onto the third bus,
wherein the third signal group includes a write enable signal.
6. The bus system according to claim 5 , wherein the fourth signal group also includes a write enable signal.
7. The bus system according to claim 5 , further comprising:
a bus slave coupled to the third bus to receive the fourth signal group.