IP Library Granted Patent US 8,049,828
Granted Patent B2
US 8,049,828 · App. 12/178,662 · Granted Nov 1, 2011

Flat-panel display device having test architecture

Assignee: AU Optronics Corp.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,049,828
App. No.
12/178,662
Granted
Nov 1, 2011
Kind
B2
Abstract

A flat-panel display device having test architecture is disclosed for disposing shorting bars without sacrificing wiring-on-array bus layout area of the outer-lead-bonding region. The flat-panel display device essentially includes a substrate having a plurality of driving integrated-circuit (IC) mounting areas, a plurality of signal lines and transmission lines disposed on the substrate, and a plurality of shorting bars disposed on the driving IC mounting areas. Each shorting bar is coupled to a corresponding signal line and a corresponding transmission line. Furthermore, in order to take out the laser-cutting process in the fabrication of the flat-panel display device for saving production cost, each driving IC mounting area is further disposed with a plurality of transistors for controlling the signal connections between the shorting bars and the signal lines, and also for controlling the signal connections between the shorting bars and the transmission lines.

Claims (29)

1. A flat-panel display device comprising:

a substrate comprising a plurality of driving IC mounting areas;

a plurality of parallel signal lines disposed on the substrate;

a plurality of transmission lines disposed on the substrate;

a plurality of shorting bars, each of the shorting bars being disposed on a corresponding driving IC mounting area of the driving IC mounting areas, the shorting bars comprising a plurality of first shorting bars and a plurality of second shorting bars;

a plurality of first transistors, each of the first transistors being disposed on a corresponding driving IC mounting area of the driving IC mounting areas, the first transistor comprising:

a first end coupled to a corresponding first shorting bar of the first shorting bars;

a second end coupled to a corresponding transmission line of the transmission lines; and

a gate coupled to a corresponding second shorting bar of the second shorting bars; and

a plurality of second transistors, each of the second transistors being disposed on a corresponding driving IC mounting area of the driving IC mounting areas, the second transistor comprising:

a first end coupled to a corresponding first shorting bar of the first shorting bars;

a second end coupled to a corresponding signal line of the signal lines; and

a gate coupled to a corresponding second shorting bar of the second shorting bars;

wherein each of the shorting bars is coupled to a corresponding signal line of the signal lines and a corresponding transmission line of the transmission lines.

2. The flat-panel display device of claim 1 , wherein the substrate further comprises a bonding area for attaching a flexible printed circuit board, the bonding area comprises a plurality of bonding pads, and at least one of the bonding pads is coupled to a corresponding transmission line of the transmission lines.

3. The flat-panel display device of claim 1 , further comprising:

at least one test pad disposed on the substrate, the test pad being coupled to a corresponding transmission line of the transmission lines.

4. The flat-panel display device of claim 1 , wherein the signal lines are a plurality of data lines or a plurality of gate lines.

5. The flat-panel display device of claim 1 , wherein the substrate further comprises an outer-lead-bonding (OLB) area, and the transmission lines are disposed on the outer-lead-bonding area of the substrate based on a wiring-on-array (WOA) arrangement.

6. The flat-panel display device of claim 1 , further comprising:

a plurality of third transistors, each of the third transistors being disposed on a corresponding driving IC mounting area of the driving IC mounting areas, the third transistor comprising:

a first end coupled to the first end of a corresponding first transistor of the first transistors;

a second end coupled to a corresponding transmission line of the transmission lines; and

a gate coupled to a corresponding second shorting bar of the second shorting bars.

7. The flat-panel display device of claim 1 , wherein the substrate further comprises a bonding area for attaching a flexible printed circuit board, the bonding area comprises a plurality of bonding pads, and at least one of the bonding pads is coupled to a corresponding transmission line of the transmission lines.

8. The flat-panel display device of claim 1 , further comprising:

at least one test pad disposed on the substrate, the test pad being coupled to a corresponding transmission line of the transmission lines.

9. The flat-panel display device of claim 1 , wherein the signal lines are a plurality of data lines or a plurality of gate lines.

10. The flat-panel display device of claim 1 , wherein the substrate further comprises an outer-lead-bonding area, and the transmission lines are disposed on the outer-lead-bonding area of the substrate based on a wiring-on-array arrangement.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2008
From: LIU, CHUN-HSIN; CHEN, YUNG-CHIH; LIU, PO-YUAN; TSAI, TSUNG-TING
To: AU OPTRONICS CORP.
Reel/Frame 021282/0679 →
Priority Claims (1)
TW 97118158 A · May 16, 2008 · national
Continuity (1)
Related Publication 20090284706A1 · Nov 19, 2009