Method of fabricating a semiconductor device having a lateral double diffused MOSFET transistor with a lightly doped source and CMOS transistor
Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. In some implementations, a method of fabricating a semiconductor device is provided that includes forming an LDMOS transistor having a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, and a first gate between the first drain and the first source on the substrate. The method also includes forming an n-type CMOS transistor having a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, and a second gate between the second drain and the second source. In so doing, the LDMOS transistor can be fabricated through a process that can be seamlessly integrated into a sub-micron CMOS process.
1. A method of fabricating a semiconductor device, the method comprising:
forming an LDMOS transistor on a substrate, the LDMOS transistor including a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, and a first gate between the first drain and the first source; and
forming an n-type CMOS transistor on the substrate, the n-type CMOS transistor including a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, and a second gate between the second drain and the second source;
wherein forming the LDMOS transistor and forming the n-type CMOS transistor comprise a first implant step that, without implanting into the first drain, simultaneously implants a first lightly n-doped region in the first source to overlap the first source-side n+ region and to extend beneath the first gate, and a second lightly n-doped region in the second drain to overlap the second drain-side n+ region and to extend beneath the second gate.
2. The method of claim 1 , wherein forming the LDMOS transistor and forming the n-type CMOS transistor comprise a second implant step that simultaneously implants the first drain-side n+ region, the first source-side n+ region, the second drain-side n+ region and the second source-side n+ region.
3. The method of claim 1 , further comprising forming a p-type CMOS transistor on the substrate, the p-type CMOS transistor including a third drain having a first drain-side p+ region, a third source having a second source-side p+ region, and a third gate between the third drain and the third source.
4. The method of claim 3 , wherein forming the LDMOS transistor and forming the p-type CMOS transistor comprise a second implant step that simultaneously implants the first source-side p+ region, the first drain-side p+ region and the second source-side p+ region.
5. The method of claim 3 , further comprising:
forming a PMOS transistor on the substrate, the PMOS transistor including a fourth drain having a second drain-side p+ region, a fourth source having a third source-side p+ region, and a fourth gate between the fourth drain and the fourth source; and
forming a NMOS transistor on the substrate, the NMOS transistor including a fifth drain having a third drain-side n+ region, a fifth source having a third source-side n+ region, and a fifth gate between the fifth drain and the fifth source.
6. The method of claim 5 , wherein forming the NMOS transistor includes forming the third drain-side n+ region and the third source-side n+ region at the same time as the first drain-side n+ region and the first source-side n+ region of the LDMOS transistor and the second drain-side n+ region and the second source-side n+ region of the n-type CMOS transistor.
7. The method of claim 5 , wherein forming the PMOS transistor includes forming the second drain-side p+ region and the third source-side p+ region at the same time as the first source-side p+ region of the LDMOS transistor and the first drain-side p+ region and the second source-side p+ region of the p-type CMOS transistor.
8. The method of claim 2 , further comprising forming a gate oxide for each of the LDMOS transistor and the n-type CMOS transistor simultaneously to provide a uniform gate oxide thickness between the LDMOS transistor and the n-type CMOS transistor.
9. The method of claim 8 , further comprising forming oxide spacers, wherein the first implant step is performed prior to forming the oxide spacers and the second implant step is performed after forming the oxide spacers.
10. The method of claim 1 , further comprising forming a gate oxide for each of the LDMOS transistor and the n-type CMOS transistor at different times and such that the LDMOS transistor is formed with a gate oxide thickness different from that of the n-type CMOS transistor.