Saving information to flash memory during power failure
An embodiment is a method and apparatus to save data during power failure. A power supply generator generates operating voltages to a circuit from a generator supply source. A power monitor monitors a normal supply voltage and a backup supply voltage to provide a normal supply voltage to the generator supply source in a normal mode and to provide a backup supply voltage to the generator supply source in a power failure mode. A data transfer circuit transfers data from a volatile memory in the circuit to a non-volatile memory during the power failure mode.
1. An apparatus comprising:
a power supply generator to generate operating voltages to a circuit from a generator supply source;
a power monitor coupled to the power supply generator to monitor a normal supply voltage and a backup supply voltage to provide the normal supply voltage to the generator supply source in a normal mode and to provide the backup supply voltage to the generator supply source in a power failure mode; and
a data transfer circuit coupled to the power monitor to transfer data from a volatile memory in the circuit to a non-volatile memory during the power failure mode.
2. The apparatus of claim 1 wherein the normal mode operates when the normal supply voltage is greater than or equal to the backup supply voltage and the power failure mode operates when the normal supply voltage is less than the backup supply voltage.
3. The apparatus of claim 1 wherein the power monitor comprises:
an OR load sharing circuit having a first input connected to a normal power circuit that generates the normal supply voltage and a second input connected to a backup power circuit that generates the backup supply voltage; and
a comparator to compare the normal supply voltage and the backup supply voltage, the comparator generating a power failure indicator in the power failure mode.
4. The apparatus of claim 3 wherein the data transfer circuit initiates transferring data from the volatile memory to the non-volatile memory when the power failure indicator is asserted.
5. The apparatus of claim 1 further comprising:
a backup power circuit coupled to the power monitor to generate the backup supply voltage.
6. The apparatus of claim 5 wherein the backup power circuit comprises:
a charging circuit coupled to a normal power circuit to provide charging current; and
a charge element coupled to the charging circuit to receive the charging current, the charge element providing the backup supply voltage in the power failure mode.
7. The apparatus of claim 3 wherein the data transfer circuit comprises:
a transfer processor to perform data transfers upon receiving the power failure indicator; and
a switching circuit coupled to the transfer processor and a main processor to switch bus signals between the transfer processor and the main processor to and from the volatile memory.
8. The apparatus of claim 1 wherein the volatile memory includes at least a synchronous dynamic random access memory (SDRAM).
9. The apparatus of claim 8 wherein the SDRAM is a double data rate (DDR), a DDR2, a DDR3, or a DDR4 SDRAM.
10. The apparatus of claim 1 wherein the non-volatile memory includes at least a flash memory.
11. A method comprising:
generating operating voltages to a circuit from a generator supply source;
monitoring a normal supply voltage and a backup supply voltage to provide the normal supply voltage to the generator supply source in a normal mode and to provide the backup supply voltage to the generator supply source in a power failure mode; and
transferring data from a volatile memory in the circuit to a non-volatile memory during the power failure mode.
12. The method of claim 11 wherein the normal mode operates when the normal supply voltage is greater than or equal to the backup supply voltage and the power failure mode operates when the normal supply voltage is less than the backup supply voltage.
13. The method of claim 11 wherein monitoring comprises:
OR load sharing from a first input connected to a normal power circuit that generates the normal supply voltage and a second input connected to a backup power circuit that generates the backup supply voltage; and
comparing the normal supply voltage and the backup supply voltage to generate a power failure indicator in the power failure mode.
14. The method of claim 13 wherein transferring comprises initiating transferring data from the volatile memory to the non-volatile memory when the power failure indicator is asserted.
15. The method of claim 11 further comprising:
generating the backup supply voltage using a backup power circuit.
16. The method of claim 15 wherein generating the backup supply voltage comprises:
providing a charging current from the normal supply voltage; and
receiving the charging current to provide the backup supply voltage in the power failure mode.
17. The method of claim 13 wherein transferring data comprises:
switching bus signals between the transfer processor and a main processor to and from the volatile memory; and
performing data transfers upon receiving the power failure indicator by a transfer processor.
18. The method of claim 11 wherein the volatile memory includes at least a synchronous dynamic random access memory (SDRAM).
19. The method of claim 18 wherein the SDRAM is a double data rate (DDR), a DDR2, a DDR3, or a DDR4 SDRAM.
20. The method of claim 11 wherein the non-volatile memory includes at least a flash memory.
21. A board assembly comprising:
a main board having a main processor; and
a data save circuit coupled to the main board comprising:
a power supply generator to generate operating voltages to a circuit from a generator supply source,
a power monitor coupled to the power supply generator to monitor a normal supply voltage and a backup supply voltage to provide the normal supply voltage to the generator supply source in a normal mode and to provide the backup supply voltage to the generator supply source in a power failure mode, and
a data transfer circuit coupled to the power monitor to transfer data from a volatile memory in the circuit to a non-volatile memory during the power failure mode.
22. The board assembly of claim 21 wherein the normal mode operates when the normal supply voltage is greater than or equal to the backup supply voltage and the power failure mode operates when the normal supply voltage is less than the backup supply voltage.
23. The board assembly of claim 21 wherein the power monitor comprises:
an OR load sharing circuit having a first input connected to a normal power circuit that generates the normal supply voltage and a second input connected to a backup power circuit that generates the backup supply voltage; and
a comparator to compare the normal supply voltage and the backup supply voltage, the comparator generating a power failure indicator in the power failure mode.
24. The board assembly of claim 23 wherein the data transfer circuit initiates transferring data from the volatile memory to the non-volatile memory when the power failure indicator is asserted.
25. The board assembly of claim 21 further comprising:
a backup power circuit coupled to the power monitor to generate the backup supply voltage.
26. The board assembly of claim 25 wherein the backup power circuit comprises:
a charging circuit coupled to a normal power circuit to provide charging current; and
a charge element coupled to the charging circuit to receive the charging current, the charge element providing the backup supply voltage in the power failure mode.
27. The board assembly of claim 23 wherein the data transfer circuit comprises:
a transfer processor to perform data transfers upon receiving the power failure indicator; and
a switching circuit coupled to the transfer processor and a main processor to switch bus signals between the transfer processor and the main processor to and from the volatile memory.
28. The board assembly of claim 21 wherein the volatile memory includes at least a synchronous dynamic random access memory (SDRAM).
29. The board assembly of claim 28 wherein the SDRAM is a double data rate (DDR), a DDR2, a DDR3, or a DDR4 SDRAM.
30. The board assembly of claim 21 wherein the non-volatile memory includes at least a flash memory.