Method of manufacturing a semiconductor device having raised source and drain of differing heights
This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions which are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region.
1. A fabrication method for a semiconductor device, comprising:
forming a gate electrode above a semiconductor substrate;
forming a silicon layer on a top surface of a first region in the semiconductor substrate adjacent one side of the gate electrode, and on a top surface of a second region in the semiconductor substrate adjacent another side of the gate electrode, wherein the first region is wider than the second region in the first region-second region direction across the gate electrode; and
forming, after forming the silicon layer by a selective epitaxial growth method, a first impurities diffusion region and a second impurities diffusion region by injecting impurities over the first region and the second region through the silicon layer,
wherein the silicon layer is formed by the selective epitaxial growth method so that the height of an upper end portion of the silicon layer at the second region is higher than the height of an upper end portion of the silicon layer at the first region, and
wherein by injecting the impurities, a depth of the second impurities diffusion region from the top surface of the semiconductor substrate is formed so as to be shallower than a depth of the first impurities diffusion region from the top surface of the semiconductor substrate.
2. The fabrication method for a semiconductor device, according to claim 1 , wherein while forming the silicon layer, the selective epitaxial growth method is used to grow the silicon layer whose thickness is controlled by controlling the size of a surface area of the semiconductor substrate where the silicon layer is grown.
3. The fabrication method for a semiconductor device, according to claim 2 , wherein the size of the surface area for the silicon layer growth is controlled by controlling the widths of the first region and the second region in the first region-second region direction across the gate electrode.
4. The fabrication method for a semiconductor device, according to claim 1 , wherein:
the gate electrode includes multiple and parallel gate electrodes; and
the widths of the first region and the second region are controlled by a gap distance between gate electrodes sandwiching the first region and a gap distance between gate electrodes sandwiching the second region.
5. The fabrication method for a semiconductor device, according to claim 4 , wherein the gap distance between gate electrodes sandwiching the first region is set so as to be wider than the gap distance between gate electrodes sandwiching the second region.
6. The fabrication method for a semiconductor device, according to claim 1 , further comprising:
forming a bit wiring so as to be connected to the first impurities diffusion region; and
forming a capacitor so as to be connected to the second impurities diffusion region.
7. The fabrication method for a semiconductor device, according to claim 1 , further comprising forming a dummy gate electrode, where no voltage is applied, so as to be adjacent to either one of the first impurities diffusion region and the second impurities diffusion region.
8. The fabrication method for a semiconductor device, according to claim 7 , further comprising forming a dielectric film so as to cover the first region, the second region, the gate electrode, and the dummy electrode.
9. The fabrication method for a semiconductor device, according to claim 1 , wherein the first region is a source region while the second region is a drain region.
10. A fabrication method for a semiconductor device, comprising:
forming a semiconductor layer that includes an active region;
forming at least one gate electrode pattern that passes over the active region to divide the active region into at least first and second regions in the active region, the first region having an upper surface that is larger in area than an upper surface of the second region;
forming an isolation region in the semiconductor layer to define the active region, the upper surface of the first region having a first peripheral edge defined by the isolation region and a second peripheral edge defined by the gate electrode pattern;
forming a dummy gate electrode pattern simultaneously with the gate electrode pattern, the dummy gate electrode pattern passing over the active region, the upper surface of the second region having a third peripheral edge defined by the isolation region, a fourth peripheral edge defined by the gate electrode pattern, and a fifth peripheral edge defined by the dummy gate electrode pattern; and
performing a selective epitaxial growth on each of the upper surfaces of the first and second regions to form a first silicon layer on the first region and a second silicon layer on the second region, the first silicon layer being smaller in thickness than the second silicon layer.
11. The fabrication method for a semiconductor device, according to claim 10 , wherein the forming the isolation region comprises forming a trench in the semiconductor layer to surround the active region and filling the trench with an insulating film.
12. The fabrication method for a semiconductor device, according to claim 10 , wherein a distance between the gate electrode pattern and the isolation region is larger than a distance between the gate electrode pattern and the dummy gate electrode pattern.
13. The fabrication method for a semiconductor device, according to claim 10 , further comprising performing an injection of impurities into the first and second regions after performing the selective epitaxial growth.
14. A method, comprising:
forming a semiconductor layer that includes an active region;
forming at least one gate electrode pattern that passes over the active region to divide the active region into at least first and second regions in the active region, the first region having an upper surface that is larger in area than an upper surface of the second region, the upper surfaces of the first and second regions being substantially coplanar with each other;
forming an isolation region in the semiconductor layer to define the active region, the upper surface of the first region having a first peripheral edge defined by the isolation region and a second peripheral edge defined by the gate electrode pattern;
forming a dummy gate electrode pattern simultaneously with the gate electrode pattern, the dummy gate electrode pattern passing over the active region, the upper surface of the second region having a third peripheral edge defined by the isolation region, a fourth peripheral edge defined by the gate electrode pattern, and a fifth peripheral edge defined by the dummy gate electrode pattern; and
performing a selective epitaxial growth on each of the upper surface of the first and second regions to form a first silicon layer on the first region and a second silicon layer on the second region, the first silicon layer being smaller in thickness than the second silicon layer.