Integrated switch
Switching between communication ports of a notebook is typically accomplished using an off-chip local area network (LAN) switch or an off-chip high speed analog multiplexer. This off-chip component is disadvantageous for several reasons, including: added cost of an additional component; increased overall power consumption because transmit amplitude loss; and reduced cable reach and link performance due to hybrid mismatch and signal distortions. To reduce cost and preserve electrical and networking performance, an integrated switch is provided to multiplex signals of a networking communication chip to multiple network paths.
1. A system comprising:
a first and a second communication port;
a sensor configured to sense whether the first or second communication port is connected to an external device; and
an integrated circuit comprising:
a media access controller (MAC);
a digital signal processing module configured to receive an information signal from the MAC and to output a processed signal;
a first analog front end (AFE) coupled to the first communication port;
a second AFE coupled to the second communication port;
a switch assembly having a first and second switch configured to receive the processed signal, the first switch being coupled to the first AFE, the second switch being coupled to the second AFE; and
a switch controller configured to delay enabling the first or second switch for a first predetermined amount of time after powering up the respective AFE based on a status of the sensor and whether the first or second communication port is active, and wherein the switch controller is configured to power off one of the AFEs having an inactive communication port;
wherein the sensor has an output coupled to the switch controller, and the output is configured to be de-bounced prior to sending the status of the sensor to the switch controller.
2. The integrated circuit of claim 1 , wherein the switch controller is configured to delay the first or second switch for a second predetermined amount of time after the first or second switch is enabled and prior to receiving the processed data from the digital signal processing module.
3. The integrated circuit of claim 1 , wherein the first predetermined amount of time is approximately 40 micro seconds.
4. The integrated circuit of claim 2 , wherein the second predetermined amount of time is approximately 10 micro seconds.
5. The integrated circuit of claim 1 , wherein the switch controller is configured to determine whether the first or second switch is properly enabled and to force the first or second switch to go into an enabled mode if the first or second switch is not properly enabled.
6. The integrated circuit of claim 1 , wherein the switch forwards the processed signal to the second AFE when the communication link at the second communication port is active.
7. The integrated circuit of claim 1 , wherein the switch forwards the processed signal to the first AFE when the communication link at the first communication port is active.
8. The integrated circuit of claim 1 , wherein the second communication port is coupled to a notebook docking station.
9. The integrated circuit of claim 1 , wherein the switch is a digital multiplexer.
10. The integrated circuit of claim 1 , wherein the first communication port is coupled to a communication connector.
11. The integrated circuit of claim 1 , wherein the first communication port is coupled to an RJ-45 connector.