IP Library › Granted Patent US 8,105,938
Granted Patent B2
US 8,105,938 · App. 12/471,771 · Granted Jan 31, 2012

Semiconductor substrate and method of manufacturing the same

Assignee: Shinko Electric Industries Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,105,938
App. No.
12/471,771
Granted
Jan 31, 2012
Kind
B2
Abstract

There is provided a method of manufacturing a semiconductor substrate. The method includes: (a) forming a wiring pattern on a substrate; (b) covering the wiring pattern with an insulating resin, thereby forming a first insulating layer; (c) forming a second insulating layer on the first insulating layer; (d) forming a plurality of grooves through the second insulating layer; (e) forming at least one via hole through the first and second insulating layers by irradiating at least one of the grooves with a laser beam; (f) forming a seed metal layer on an inner surface of the at least one via hole, inner surfaces of the grooves, and a surface of the second insulating layer; and (g) forming a plating layer in the at least one via hole and the grooves, by an electrolytic plating using the seed metal layer as a power feeding layer.

Claims (27)

1. A method of manufacturing a semiconductor substrate, the method comprising:

(a) forming a first wiring pattern on a substrate;

(b) covering the first wiring pattern with an insulating resin, thereby forming a first insulating layer;

(c) forming a second insulating layer on the first insulating layer;

(d) forming a plurality of grooves through only a top surface of the second insulating layer to expose a top surface of the first insulating layer;

(e) forming at least one via hole through the first and second insulating layers by irradiating at least a portion of the plurality of grooves with a laser beam while another portion of the plurality of grooves extend only through the top surface of the second insulating layer to the top surface of the first insulating layer;

(f) forming a seed metal layer on an inner surface of the at least one via hole, inner surfaces of the grooves, and a surface of the second insulating layer; and

(g) forming a plating layer in the at least one via hole to form a through via and the grooves to form a second wiring layer, by an electrolytic plating using the seed metal layer as a power feeding layer, wherein the second wiring layer contacts the surface of the first insulating layer; and

(h) polishing the plating layer until the seed metal layer on the surface of the second insulating layer is removed,

wherein after step (h), surfaces of the through via and the second wiring layer are flush with the surface of the second insulating layer, and

wherein a diameter of a portion of the at least one via hole in the second insulating layer is the same as a diameter of a portion of the at least one via hole in the first insulating layer.

2. The method according to claim 1 , wherein step (g) comprises: forming the plating layer such that the plating layer covers the surface of the second insulating layer.

3. The method according to claim 1 , wherein the second insulating layer is made of a photosensitive resin material, and

wherein step (d) comprises forming the grooves by exposing and developing the second insulating layer.

4. The method according to claim 1 , wherein step (d) comprises:

forming a plurality of grooves through the second insulating layer, viewing the plurality of grooves, and calculating a via forming position based on a pattern of the grooves.

5. A semiconductor substrate, comprising:

a substrate;

a first wiring pattern formed on the substrate;

a first insulating layer covering the first wiring pattern;

a second insulating layer formed on the first insulating layer and comprising a plurality of grooves formed through only a top surface of the second insulating layer to a top surface of the first insulating layer;

a plurality of second wiring patterns filled in the plurality of grooves, wherein the plurality of second wiring patterns contacts the surface of the first insulating layer;

a through via formed through the first and second insulating layers and which electrically connects the first wiring pattern to the second wiring patterns, wherein a side wall of the through via is uniform at a boundary between the first insulating layer and the second insulating layer,

wherein surfaces of the through via and the second wiring patterns are flush with a surface of the second insulating layer,

wherein a first portion of the plurality of grooves are formed through only the top surface of the second insulating layer to the top surface of the first insulating layer and a second portion of the plurality of grooves are irradiated to form the through via, and

wherein a diameter of a portion of the through via in the second insulating layer is the same as a diameter of a portion of the through via in the first insulating layer.

6. The semiconductor substrate according to claim 5 , wherein the second insulating layer is made of a photosensitive resin.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2009
From: ITO, HITOSHI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 022734/0130 →
Priority Claims (1)
JP 2008-139155 · May 28, 2008 · national
Continuity (1)
Related Publication 20090294979A1 · Dec 3, 2009