Method of designing semiconductor device and method of manufacturing the same
A semiconductor device includes a capacitor including a lower electrode and a upper electrode, and a capacitive film formed therebetween; a first via group including one or more first vias which is electrically connected to the lower electrode; and a second via group including one or more second vias which is electrically connected to the upper electrode and formed simultaneously with the first via group. The semiconductor device is designed by a method including a step of setting the number of the first vias and the second vias so that a value obtained by dividing a capacitance value of the capacitor by the total number of the first vias and the second vias included in the first via group and the second via group is set to be equal to or less than a predetermined value.
1. A method of designing a semiconductor device which includes:
a capacitor including a first electrode and a second electrode formed over a substrate, and a capacitive film formed between said first electrode and said second electrode;
a first via group including one or more first vias which is formed over said substrate, electrically connected to said first electrode, and formed simultaneously with each other; and
a second via group including one or more second vias which is formed over said substrate, electrically connected to said second electrode, and formed simultaneously with said first via group,
said method comprising:
setting the number of said first vias and said second vias so that a value obtained by dividing a capacitance value of said capacitor by the total number of said first vias and said second vias included in said first via group and said second via group is set to be equal to or less than a predetermined value.
2. The method of designing the semiconductor device as set forth in claim 1 ,
wherein said predetermined value is a capacitance value of the range in which high-resistance failure of the via is not generated.
3. The method of designing the semiconductor device as set forth in claim 1 ,
wherein said predetei mined value is 8 pF.
4. The method of designing the semiconductor device as set forth in claim 1 ,
wherein said step of setting the number of said first vias and said second vias is performed when a barrier metal film exists directly below said first via group or said second via group.
5. The method of designing the semiconductor device as set forth in claim 4 ,
wherein said barrier metal film is made of a Ti film, a TiN film, or a stacked fil thereof.
6. The method of designing the semiconductor device as set forth in claim 1 ,
wherein said capacitor is constituted by a lower electrode, a capacitive film, and an upper electrode stacked in this order.
7. The method of designing the semiconductor device as set forth in claim 1 ,
wherein said capacitor is constituted by a first interconnect and a second interconnect formed in the same layer, and an insulating film disposed between the first interconnect and the second interconnect.
8. A method of manufacturing the semiconductor device designed by the method of designing the semiconductor device as set forth in claim 1 ,
said method of manufacturing comprising:
simultaneously forming via holes for forming vias which are constituted by said first via group and said second via group.