Semiconductor storage device
A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region ( 7 ) where DRAM cells are formed is defined by an isolation trench ( 40 ) formed in a silicon substrate ( 1 ). The isolation trench ( 40 ) has an isolation insulating film ( 4 ) formed therein. Each DRAM cell includes a MOS transistor having a gate electrode ( 12 ) with sidewalls ( 13 ), and a capacitor having an upper electrode ( 22 ) with sidewalls ( 23 ). A recess ( 41 ) is formed in the upper portion of the isolation trench ( 40 ), and the upper electrode ( 22 ) of the capacitor has a buried portion buried in the recess ( 41 ). The outer edge (E 1 ) of the buried portion of the upper electrode ( 22 ) is located inside the outer edge (E 2 ) of the sidewalls ( 23 ).
1. A semiconductor storage device comprising:
an active region defined by a trench formed in an upper portion of a semiconductor substrate and where a memory cell is formed;
an element isolation insulating film formed in said trench;
a MOS transistor formed in said active region; and
a capacitor having a lower electrode which is an impurity diffusion layer connected to a source or drain region of said MOS transistor, a dielectric layer formed on a surface of said impurity diffusion layer, and an upper electrode formed on said dielectric layer, wherein
said element isolation insulating film having a recess therein between adjacent memory cells in an extended direction of a gate electrode of said MOS transistor which exposes an inner wall of said trench,
said impurity diffusion layer and said dielectric layer extend from an upper surface of said active region along the inner wall of said trench which is exposed in said recess,
said upper electrode has a first portion buried in said recess and a second portion which is not buried in said recess,
said second portion extends closer to a gate electrode of said MOS transistor than said recess at an element isolation region between adjacent memory cells in the extended direction of said gate electrode in a cross-sectional view perpendicular to the extended direction of said gate electrode, and
a step is formed in a portion of the lower electrode and dielectric layer underlying the second portion of the upper electrode.
2. The semiconductor storage device according to claim 1 , wherein a silicide layer is formed on an upper surface of said source or drain region connected to said lower electrode, between said gate electrode and said upper electrode.
3. The semiconductor storage device according to claim 2 ,
wherein a second silicide layer is formed on said upper electrode.
4. The semiconductor storage device according to claim 3 ,
wherein said first silicide layer and said second silicide layer include a same metal.
5. The semiconductor storage device according to claim 1 ,
wherein said dielectric layer and a gate oxide film of said MOS transistor are formed in the same process step.
6. The semiconductor storage device according to claim 1 , further comprising:
a sidewall formed on a side surface of said upper electrode and on said dielectric layer.
7. A semiconductor storage device comprising:
an active region defined by a trench formed in an upper portion of a semiconductor substrate and where a memory cell is formed;
an element isolation insulating film formed in said trench;
a MOS transistor formed in said active region; and
a capacitor having a lower electrode which is an impurity diffusion layer connected to a source or drain region of said MOS transistor, a dielectric layer formed on a surface of said impurity diffusion layer, and an upper electrode formed on said dielectric layer, wherein
said element isolation insulating film having a recess therein between adjacent memory cells in an extended direction of a gate electrode of said MOS transistor which exposes an inner wall of said trench,
said impurity diffusion layer and said dielectric layer extend from an upper surface of said active region along the inner wall of said trench which is exposed in said recess,
said upper electrode has a first portion buried in said recess and a second portion which is not buried in said recess, and
an outer edge of said second portion near said gate electrode extends closer to said gate electrode than said recess at an element isolation region between adjacent memory cells in the extended direction of said gate electrode in a cross-sectional view perpendicular to the extended direction of said gate electrode, and
a step is formed in a portion of the lower electrode and dielectric layer underlying the second of the upper electrode.
8. The semiconductor storage device according to claim 7 ,
wherein a first silicide layer is formed on an upper surface of said source or drain region connected to said lower electrode, between said gate electrode and said upper electrode.
9. The semiconductor storage device according to claim 7 , further comprising:
a sidewall formed on a side surface of said upper electrode and on said dielectric layer.