Semiconductor integrated circuit device
To generate a highly accurate SSC while reducing the circuit area of a clock generation circuit that generates a normal clock and an SSC. A clock signal output from a voltage controlled oscillator is frequency-divided by a frequency divider, and is output as a first frequency-divided clock to a selector. The frequency divider outputs a plurality of second frequency-divided clocks each shifted in phase by 1/m of a period based on a control signal of a control circuit. The selector selects two frequency-divided clocks having the closest phase shift from among the first and second frequency-divided clocks. Based on a weighting data signal output from the control circuit, a phase interpolation circuit phase-shifts the frequency-divided clock by a phase shift obtained by dividing the phase difference between the two frequency-divided clocks, and outputs the resultant clock as an output clock.
1. A semiconductor integrated circuit device comprising a clock generation circuit that includes:
a PLL generating a first clock signal equal in frequency to a reference clock signal and a plurality of second clock signals each arbitrarily shifted in phase from the first clock signal; and
a spread spectrum clock generator generating a frequency modulation clock signal which modulates the frequencies of the first and second clock signals generated by the PLL to spread an electromagnetic spectrum,
wherein the spread spectrum clock generator includes:
a frequency divider that frequency-divides the first clock signal output from the PLL;
a frequency-divided clock generator that outputs a frequency-divided signal frequency-divided by the frequency divider based on the phase-shifted second clock signals output from the PLL to generate phase-shifted multiphase frequency-divided clocks;
a frequency-divided clock selector that selects and outputs any two frequency-divided clocks whose phases are different from and closest to each other from among the multiphase frequency-divided clocks generated by the frequency-divided clock generator;
a phase interpolation circuit that phase-shifts the frequency-divided clock by a phase shift obtained by dividing the phase difference between the two frequency-divided clocks from the two frequency-divided clocks selected by the frequency-divided clock selector and that outputs the resultant clock as the frequency modulation clock signal; and
a control circuit that controls the frequency-divided clock selector and the phase interpolation circuit such that a period of the frequency modulation clock signal output from the phase interpolation circuit differs from a period of the first clock signal output form the PLL.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the control circuit outputs to the frequency-divided clock selector a selection signal that controls so as to select and output any two frequency-divided clocks from among the multiphase frequency-divided clocks output from the frequency-divided clock generator, outputs to the phase interpolation circuit weighting data for the phase interpolation circuit to divide the phase difference between the frequency-divided clocks output from the frequency-divided clock selector, and performs control so that the frequency modulation clock output from the phase interpolation circuit changes a frequency thereof at any period.
3. The semiconductor integrated circuit device according to claim 1 ,
wherein the frequency divider arbitrarily switches a frequency division ratio based on a frequency-division-ratio switching signal output from the control signal, and
wherein the control circuit controls so as to switch the frequency division ratio each time the phase shift of the frequency modulation clock output from the phase interpolation circuit exceeds one period of the first clock signal output from the PLL.
4. The semiconductor integrated circuit device according to claim 1 ,
wherein the control circuit operates in synchronization with the most delayed frequency-divided clock among the multiphase frequency-divided clocks output from the frequency-divided clock generator.
5. The semiconductor integrated circuit device according to claim 2 ,
wherein the frequency divider arbitrarily switches a frequency division ratio based on a frequency-division-ratio switching signal output from the control signal, and
wherein the control circuit controls so as to switch the frequency division ratio each time the phase shift of the frequency modulation clock output from the phase interpolation circuit exceeds one period of the first clock signal output from the PLL.
6. The semiconductor integrated circuit device according to claim 2 ,
wherein the control circuit operates in synchronization with the most delayed frequency-divided clock among the multiphase frequency-divided clocks output from the frequency-divided clock generator.
7. The semiconductor integrated circuit device according to claim 3 ,
wherein the control circuit operates in synchronization with the most delayed frequency-divided clock among the multiphase frequency-divided clocks output from the frequency-divided clock generator.