Method of manufacturing power semiconductor device

1. A method of manufacturing a power semiconductor device, comprising:

preparing a semiconductor substrate having one main surface and an other main surface, and including a first layer having a first conductivity type and located at a side of said one main surface;

forming a mask layer having a plurality of openings on said first layer;

forming a second layer having a second conductivity type different from said first conductivity type on said first layer by introducing impurities using said mask layer;

forming a third layer having said first conductivity type on said second layer by introducing impurities using said mask layer;

forming a trench extending through said second layer and said third layer to said first layer by carrying out etching using an etching mask including at least said mask layer;

forming a gate insulation film covering a sidewall of said trench;

forming a trench gate filling said trench on said gate insulation film; and

after said forming said second layer, forming a sidewall film on a sidewall of said mask layer in order to narrow said plurality of openings, wherein said etching mask includes said sidewall film.

2. The method of manufacturing a power semiconductor device according to claim 1 , wherein said forming said second layer comprises forming a high concentration region which is higher in impurity concentration at a surface side than said second layer by introducing impurities from each of a pair of openings adjacent to each other among said plurality of openings into a region of said first layer covered with said mask layer.

3. The method of manufacturing a power semiconductor device according to claim 1 , wherein

said plurality of openings of said mask layer are arranged at a pitch in one direction and each have a width in said one direction, and

said pitch is smaller than a sum of said width and a value of 1.6 times of a diffusion depth of said second layer.

4. The method of manufacturing a power semiconductor device according to claim 1 , further comprising forming a semiconductor region having said second conductivity type on said other main surface of said semiconductor substrate.

5. The method of manufacturing a power semiconductor device according to claim 4 , further comprising forming a carrier accumulation layer having said first conductivity type on said first layer by introducing impurities using said mask layer, wherein

said forming said second layer is performed by forming said second layer on said first layer with said carrier accumulation layer interposed there between.

6. The method of manufacturing a power semiconductor device according to claim 5 , wherein said forming said carrier accumulation layer is performed using an ion implanter.

7. The method of manufacturing a power semiconductor device according to claim 1 , wherein said semiconductor substrate includes a semiconductor region having said second conductivity type and located at a side of said other main surface.

8. The method of manufacturing a power semiconductor device according to claim 7 , further comprising forming a carrier accumulation layer having said first conductivity type on said first layer by introducing impurities using said mask layer, wherein

said forming said second layer is performed by forming said second layer on said first layer with said carrier accumulation layer interposed there between.

9. The method of manufacturing a power semiconductor device according to claim 8 , wherein said forming said carrier accumulation layer is performed using an ion implanter.