IP Library › Granted Patent US 8,130,892
Granted Patent B2
US 8,130,892 · App. 12/171,800 · Granted Mar 6, 2012

ADPLL frequency synthesizer

Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,130,892
App. No.
12/171,800
Granted
Mar 6, 2012
Kind
B2
Abstract

In an ADPLL frequency synthesizer where a frequency control word is changed from FCW 0 to FCW 2 , a control sensitivity estimation section firstly measures oscillatory frequencies f 1 L and f 1 H obtained, respectively, when frequency control words FCW 1 L and FCW 1 H being used as dummies are set, and then measures an oscillatory frequency f 2 obtained when a frequency control word FCW 2 is set. Thereafter, based on values of the oscillatory frequencies f 1 L , f 1 H and f 2 , the control sensitivity estimation section calculates a control sensitivity K DCO 2 obtained when the frequency control word FCW 2 is set. Based on a value of the control sensitivity K DCO 2 , the loop filter determines values of filter coefficients α 2 and ρ 2 so as to be equal to a natural frequency ω n and a damping factor ζ, respectively, both of which have been previously designed.

Claims (14)

1. An ADPLL frequency synthesizer comprising:

a digital controlled oscillator operable to output a signal having a predetermined oscillatory frequency;

a digital phase comparator operable to compare a phase of the oscillatory frequency of the digital controlled oscillator with a reference phase and operable to generate a phase error signal representing a difference between the phase of the oscillatory frequency of the digital controlled oscillator and the reference phase;

a loop filter operable to control the oscillatory frequency of the digital controlled oscillator based on the phase error signal generated by the digital phase comparator; and

a control sensitivity estimation section operable to estimate a control sensitivity of the digital controlled oscillator,

wherein the control sensitivity estimation section calculates two control sensitivities at dummy frequencies which are, respectively, lower and higher than an oscillatory frequency to be set, so as to estimate a mean value of the calculated two control sensitivities as a first control sensitivity, and to estimate a second control sensitivity at the oscillatory frequency to be set, and

wherein the loop filter updates a filter coefficient based on the first and second control sensitivities.

2. The ADPLL frequency synthesizer according to claim 1 ,

wherein the control sensitivity estimation section estimates the first and second control sensitivities only once each time the oscillatory frequency of the digital controlled oscillator is changed.

3. A radio communication device comprising:

an antenna;

a transmitting device operable to transmit a radio signal via the antenna;

a receiving device operable to receive a radio signal via the antenna; and

an ADPLL frequency synthesizer, according to claim 1 , operable to provide a signal to each of the transmitting device and the receiving device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2008
From: TAKAHASHI, KENJI
To: PANASONIC CORPORATION
Reel/Frame 021793/0847 →
Priority Claims (1)
JP 2007-184865 · Jul 13, 2007 · national
Continuity (1)
Related Publication 20090052508A1 · Feb 26, 2009