Semiconductor memory device for byte-based masking operation and method of generating parity data
A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.
1. A semiconductor memory device comprising:
a memory cell array that stores bits of normal data and parity data therein;
an error correction code (ECC) engine that calculates the parity data using the normal data;
a mode selection unit that selects one of a masking mode and a normal mode in response to a mode selection signal;
a first column selection line for updating a first section of the normal data; and
a second column selection line for reading a second section of the normal data,
wherein the ECC engine calculates the parity data using the normal data that includes the first section that is to be updated and the second section that is to be saved by a masking operation during the masking mode in which the masking operation is performed,
wherein the ECC engine reads the second section when the mode selection signal is enabled to select the masking mode,
wherein the mode selection signal is enabled before a masking signal is enabled, thereby indicating that the masking mode is activated, and
wherein the second column selection line is enabled before the first column selection line is enabled when the mode selection signal is enabled.
2. The semiconductor memory device of claim 1 , wherein the ECC engine reads the second section before updating the first section of the normal data.
3. The semiconductor memory device of claim 1 , wherein the ECC engine transmits the calculated parity data to the memory cell array.
4. The semiconductor memory device of claim 1 , wherein the mode selection signal is generated using a column address of the semiconductor memory device.
5. The semiconductor memory device of claim 1 , wherein the mode selection signal is applied through a control pin of the semiconductor memory device.
6. The semiconductor memory device of claim 1 , wherein, in the masking mode, the masking operation is performed on an 8-bit basis.
7. The semiconductor memory device of claim 1 , wherein the normal data is 16 bits.
8. The semiconductor memory device of claim 7 , wherein the first section or the second section of the normal data is 8 bits.
9. The semiconductor memory device of claim 7 , wherein the first section is the first eight bits of the normal data and the second section is the last eight bits of the normal data.
10. The semiconductor memory device of claim 7 , wherein the first section is the last eight bits of the normal data and the second section is the first eight bits of the normal data.
11. The semiconductor memory device of claim 1 , wherein the ECC engine calculates the parity data using the normal data that is to be updated in the normal mode.
12. The semiconductor memory device of claim 1 , wherein the ECC engine uses a hamming code.
13. A method of generating parity data in a semiconductor memory device that includes a memory cell array that stores bits of normal data and the parity data, the method comprising:
selecting one of a masking mode and a normal mode in response to a mode selection signal;
dividing the normal data into a first section that is to be updated and a second section that is to be saved by a masking operation during the masking mode in which the masking operation is performed;
enabling a second column selection line for reading the second section before enabling a first column selection line for updating the first section of the normal data when the mode selection signal is enabled;
reading the second section of the normal data when the mode selection signal is enabled to select the masking mode and when the second column selection line is enabled; and
calculating the parity data using the first and second sections,
wherein the mode selection signal is enabled before a masking signal is enabled, thereby indicating that the masking mode is activated.
14. The method of claim 13 , further comprising: reading the second section before updating the first section of the normal data.
15. The method of claim 13 , further comprising: transmitting the calculated parity data to the memory cell array.
16. The method of claim 13 , wherein the mode selection signal is generated using a column address of the semiconductor memory device.
17. The method of claim 13 , wherein the mode selection signal is applied through a control pin of the semiconductor memory device.
18. The method of claim 13 , wherein, in the masking mode, the masking operation is performed on an 8-bit basis.
19. The method of claim 13 , further comprising: calculating the parity data using the normal data that is to be updated in the normal mode.