Semiconductor device with an electrode as an alignment mark, and method of manufacturing the same

1. A semiconductor device comprising:

a semiconductor substrate;

a back side drawn electrode formed by embedding a first conductive material in a contact hole penetrating the semiconductor substrate through an insulating film formed to include a uniform thickness, used also as an alignment mark, and configured to draw out an electrode to the back side of the semiconductor substrate; and

a pad provided on the back side of the semiconductor substrate, and connected to the back side drawn electrode,

wherein the electrode includes a second conductive material having a resistance which is lower than that of the first conductive material.

2. The device of claim 1 further comprising a backside illumination CMOS image sensor in which a sensor section is provided on the surface side of the semiconductor substrate, and the backside illumination CMOS image sensor including lens formed by using the back side drawn electrode as the alignment mark is provided on the back side of the semiconductor substrate opposed to the surface side.

3. The device of claim 1 , wherein each of the electrode and pad contains a third conductive material resistance of which is lower than the first conductive material.

4. The device of claim 3 , wherein

the first conductive material is polysilicon to which impurities are added,

second conductive material is tungsten, and

third conductive material is copper.

5. The device of claim 1 further comprising a contact connected to the electrode.

6. The device of claim 5 further comprising:

wiring and vias of a plurality of layers electrically connected to the contact; and

a wiring layer electrically connected to the wiring and vias of the plurality of layers.

7. A method of manufacturing a semiconductor device configured to form a back side drawn electrode which is used to draw out an electrode used also as an alignment mark to the back side of a semiconductor substrate comprising:

forming a through hole in the semiconductor substrate;

forming an insulating film with a uniform thickness on an inner wall of the through hole; and

embedding a first conductive material in the through hole through the insulating film to thereby form a contact layer.

8. The method of claim 7 further comprising forming, after forming the contact layer, a back side illumination CMOS image sensor provided with a sensor section and a lens, the sensor section formed on the surface side of the semiconductor substrate, and the lens formed on the back side of the semiconductor substrate opposed to the surface side by using the back side drawn electrode as an alignment mark.

9. The method of claim 7 , wherein forming the contact layer includes replacing the first conductive material embedded in the through hole with a second conductive material resistance of which is lower than the first conductive material.

10. The method of claim 7 wherein the forming the contact layer includes replacing the first conductive material embedded in the through hole with a second conductive material resistance of which is lower than the first conductive material, and

further comprising forming, by using the second conductive material, a pad connected to the contact layer on the back side of the semiconductor substrate.

11. The method of claim 10 , wherein the contact layer and pad are simultaneously formed.

12. The method of claim 11 , wherein simultaneously forming the contact layer and pad includes using a third conductive material resistance of which is lower than the first conductive material.

13. The method of claim 12 , wherein

the first conductive material is polysilicon to which impurities are added,

second conductive material is tungsten, and

third conductive material is copper.

14. The method of claim 7 , further comprising forming a contact electrically connected to the contact layer.

15. The method of claim 14 , further comprising:

forming wiring and vias of a plurality of layers electrically connected to the contact; and

forming a wiring layer electrically connected to the wiring and vias of the plurality of layers.