High planarizing method for use in a gate last process

1. A method for performing a chemical-mechanical polishing (CMP), comprising:

processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form an interlayer dielectric (ILD) layer over the hard mask;

performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer;

performing a second CMP process with a second slurry to remove the hard mask; and

performing a third CMP process with a third slurry to remove an interfacial that forms between the dummy gate and hard mask during the semiconductor processing.

2. The method of claim 1 , wherein the first slurry includes silica (SiO 2 ) with a percentage ranging from about 10% to about 25%, and a pH ranging from about 9 to about 12.

3. The method of claim 2 , wherein the first CMP process includes one of a slurry distribution of about 250 ml/min, a rotational speed ranging from about 80 to about 120 rpm, a polishing pressure ranging from about 1.5 to about 5 psi, and a time period ranging from about 60 to about 90 seconds.

4. The method of claim 2 , wherein the first slurry has no selectivity.

5. The method of claim 1 , wherein the second slurry includes cerium oxide (CeO 2 ) having a percentage ranging from about 0.1% to about 8%, and a pH ranging from about 4 to about 10.

6. The method of claim 4 , wherein the second CMP process includes one of a slurry distribution of about 250 ml/min, a rotational speed ranging from about 60 to about 120 rpm, a polishing pressure ranging from about 1.5 to about 5 psi, and a time period ranging from about 200 to about 400 seconds.

7. The method of claim 4 , wherein the second slurry has a selectivity that is greater than about 20.

8. The method of claim 1 , wherein the third slurry includes silica (SiO 2 ) having a percentage ranging from about 0.5% to about 12%, and a pH ranging from about 9 to about 12.

9. The method of claim 6 , wherein the third CMP process includes one of a slurry distribution of about 250 ml/min, a rotational speed ranging from about 40 to about 90 rpm, a polishing pressure ranging from about 0.3 to about 3 psi, and a time period ranging from about 5 to about 15 seconds.

10. The method of claim 6 , wherein the third slurry has a selectivity that is greater than about 3.

11. A method for performing a chemical-mechanical polishing (CMP) on a semiconductor substrate having a dummy gate formed thereon, a hard mask formed on the dummy gate, and a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer formed over the hard mask, the method comprising:

performing a first CMP process with a first slurry to planarize the ILD layer;

performing a second CMP process with a second slurry to remove the CESL and the hard mask; and

performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.

12. The method of claim 11 , wherein the first slurry includes silica (SiO 2 ) with a percentage ranging from about 10% to about 25%, and a pH ranging from about 9 to about 12.

13. The method of claim 11 , wherein the second slurry includes cerium oxide (CeO 2 ) having a percentage ranging from about 0.1% to about 8%, and a pH ranging from about 4 to about 10.

14. The method of claim 11 , wherein the third slurry includes silica (SiO 2 ) having a percentage ranging from about 0.5% to about 12%, and a pH ranging from about 9 to about 12.

15. The method of claim 11 , wherein the first, second, and third slurries each include one of an organic acid, EDTA, surfactant, chelating agent, acid/alkali buffer, ionic strength agent, C-rich surfactant, F-rich surfactant, and OH-rich surfactant.

16. The method of claim 11 , further comprising, after performing the third CMP process, removing the dummy gate and replacing it with a metal gate.

17. A method for performing a multi-platen chemical mechanical polishing (CMP), comprising:

processing a semiconductor substrate to form a dummy gate on the substrate, to form a hard mask on the dummy gate, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over the substrate including the hard mask;

performing a first CMP process to planarize the ILD layer, the first CMP process using a first platen and a first slurry;

performing a second CMP process to remove the CESL and hard mask, the second CMP using a second platen and a second slurry, the second slurry having a selectivity greater than about 20; and

performing a third CMP process to remove an interfacial layer that forms between the dummy gate and hard mask during the semiconductor processing, the third CMP using a third platen and a third slurry, the third slurry having a selectivity greater than about 3.

18. The method of claim 17 , wherein the second slurry has the selectivity with respect to an oxide and a nitride.

19. The method of claim 17 , wherein the third slurry has the selectivity with respect to a polysilicon and an oxide.

20. The method of claim 17 , wherein:

the first slurry includes silica (SiO 2 ) with a percentage ranging from about 10% to about 25%, and a pH ranging from about 9 to about 12;

the second slurry includes cerium oxide (CeO 2 ) having a percentage ranging from about 0.1% to about 8%, and a pH ranging from about 4 to about 10; and

the third slurry includes silica (SiO 2 ) having a percentage ranging from about 0.5% to about 12%, and a pH ranging from about 9 to about 12.