Semiconductor device and method of manufacturing the same

1. A method of manufacturing an insulation layer of a semiconductor device including double insulation layers, a formation of the double insulation layers comprising:

coating a first insulation layer on an entire surface of a substrate;

coating a second insulation layer directly on the first coated insulation layer for an entire surface of the substrate, the second insulation layer including a photosensitive material and being formed of a material differing from that of the first insulation layer;

patterning the second insulation layer to form a first region, a second region, and a third region, wherein, in the first region, the second insulation layer is formed to have a first pattern of a first thickness, wherein, in the second region, the second insulation layer is formed to have a second pattern of a second thickness less than the first thickness, and wherein, in the third region, the second insulation layer is removed to expose the first insulation layer formed at a lower portion of the second insulation layer;

etching the first insulation layer of the third region;

removing the second pattern of the second insulation layer such that the first insulation layer remains in the second region on at least substantially an entire length of a wiring that extends substantially from one end of the substrate to another end of the substrate; and

ashing the first pattern of the second insulation layer such that the first pattern of the second insulation layer remains as one of the double insulation layers in at least the first region of the semiconductor device.

2. The method as claimed in claim 1 , wherein the patterning of the second insulation layer comprises exposing and developing the second insulation layer using a developing light and a half tone mask having different light-shielding degrees according to different regions.

3. The method as claimed in claim 2 , wherein the half tone mask includes a light-shielding pattern corresponding to the first region, a partial light-shielding pattern corresponding to the second region, and an opening pattern corresponding to the third region.

4. The method as claimed in claim 1 , wherein after the etching, removing, and ashing, a thickness of the double insulation layers remaining in the first region is substantially equal to a thickness of the first insulation layer plus a thickness of the ashed second insulation layer, a thickness of the double insulation layers remaining in the second region is substantially equal to the thickness of the first insulation layer, and wherein the first insulation layer and the second insulation layer have been substantially removed in the third region.

5. The method as claimed in claim 1 , wherein the etching of the first insulation layer of the third region exposes a layer under the first insulation layer in the third region.

6. A method of manufacturing an organic light emitting display including a display region formed on a substrate; a non-display region being electrically connected to the display region in which at least one terminal is formed; and double insulation layers, a formation of the double insulation layers comprising:

forming a first insulation layer;

forming a second insulation layer directly on the first insulation layer for at east the entire display region, the second insulation layer including a photosensitive material and being formed of a material differing from that of the first insulation layer;

patterning the second insulation layer to form a first region, a second region, and a third region, wherein, in the first region, the second insulation layer is formed to have a first pattern of a first thickness, wherein, in the second region, the second insulation layer is formed to have a second pattern of a second thickness less than the first thickness, and wherein, in the third region, the second insulation layer is removed to expose the first insulation layer formed at a lower portion of the second insulation layer;

etching the first insulation layer of the third region;

removing the second pattern of the second insulation layer such that the first insulation layer remains in the second region on at least substantially an entire length of a wiring that extends substantially from one end of the substrate to another end of the substrate; and

ashing the first pattern of the second insulation layer such that the first pattern of the second insulation layer remains as one of the double insulation layers in at least the first region of the semiconductor device.

7. The method as claimed in claim 6 , wherein the patterning of the second insulation layer comprises exposing and developing the second insulation layer using a developing light and a half tone mask having different light-shielding degrees according to different regions.

8. The method as claimed in claim 7 , wherein the half tone mask includes a light-shielding pattern corresponding to the first region, a partial light-shielding pattern corresponding to the second region, and an opening pattern corresponding to the third region.

9. The method as claimed in claim 6 , wherein after the etching, removing, and ashing, a thickness of the double insulation layers remaining in the first region is substantially equal to a thickness of the first insulation layer plus a thickness of the ashed second insulation layer, a thickness of the double insulation layers remaining in the second region is substantially equal to the thickness of the first insulation layer, and wherein the first insulation layer and the second insulation layer have been substantially removed in the third region.

10. The method as claimed in claim 6 , wherein the etching of the first insulation layer of the third region exposes a layer under the first insulation layer in the third region.