Apparatus and method for driving liquid crystal display
A apparatus and method for driving a liquid crystal display that minimizes the generation of electro-magnetic interference (EMI) in a cost effective manner includes a gate control signal generator that generates a gate control signal using a externally inputted synchronizing signal, a data control signal generator that generates a data control signal using the synchronizing signal, a data aligner that re-aligns externally inputted video data, a plurality of buffers at output terminals of the gate control signal generator, the data control signal generator and the data aligner, and a control unit that applies control signals to the buffers to control current values of signals outputted by the buffers.
1. A driving apparatus for a liquid crystal display, comprising:
a gate control signal generator that generates gate control signals using an externally inputted synchronizing signal;
a data control signal generator that generates data control signals using the synchronizing signal;
a data aligner that re-aligns externally inputted data;
a plurality of buffers provided at output terminals of the gate control signal generator, the data control signal generator, and the data aligner;
a control unit that applies control signals to the plurality of buffers to control characteristics of signals outputted by the plurality of buffers;
wherein said gate control signal generator, said data control signal generator, said data aligner, and said buffers are within an interior of a timing controller; and
wherein said control unit is exterior to the timing controller;
wherein said plurality of buffers includes:
a first buffer that receives the gate control signals outputted from the gate control signal generator as having a rectangular waveform and outputs the received gate control signals as having a sloped waveform in accordance with a first control signal outputted by the control unit,
wherein the gate control signals output from the first buffer are directly supplied to a gate driver;
a second buffer that receives the data control signals outputted from the data control signal generator as having a rectangular waveform and outputs the received data control signals as having a sloped waveform in accordance with a second control signal outputted by the control unit,
wherein the data control signals output from the second buffer are directly supplied to a data driver;
a third buffer that receives the re-aligned data outputted from the data aligner as having a rectangular waveform and outputs the received data as having a sloped waveform in accordance with a third control signal outputted by the control unit, wherein the data output from the third buffer are directly supplied to the data driver;
wherein edges of the sloped waveform are formed of round shape;
wherein the gate control signals outputted by the gate control signal generator have a rectangular waveform and a first current value of 10 mA, and the control unit outputs the first control signal to the first buffer such that gate control signals having a sloped waveform and having a second current value of 8 mA or 6 mA are outputted to the gate driver;
wherein the data control signals outputted by the data control signal generator have a rectangular waveform and a first current value of 8 mA, and the control unit outputs the second control signal to the second buffer such that data control signals having a sloped waveform and having a second current value of 6 mA are outputted to the data driver;
wherein the data outputted by the data aligner have a rectangular waveform and a first current value of 12 mA, and the control unit outputs the third control signal to the third buffer such that data having a sloped waveform and having a second current value of 10 mA, 8 mA, or 6 mA are outputted to the data driver.
2. A timing controller of a driving apparatus, comprising:
a control unit;
a gate control signal generator connected to the control unit, wherein the gate control signal generator generates gate control signals;
a data control signal generator connected to the control unit, wherein the data control signal generator generates data control signals;
a data aligner connected to the control unit, wherein the data aligner re-aligns externally inputted data;
a control signal generator generating a plurality of control signals;
a first buffer connected between the gate control signal generator and a gate driver of a display, wherein the first buffer receives the gate control signals outputted from the gate control signal generator as having a rectangular waveform and outputs the received gate control signals as having a sloped waveform in accordance with a first control signal outputted by the control signal generator, wherein the gate control signals output from the first buffer are directly supplied to the gate driver;
a second buffer connected between the data control signal generator and a data driver of a display, wherein the second buffer receives the data control signals outputted from the data control signal generator as having a rectangular waveform and outputs the received data control signals as having a sloped waveform in accordance with a second control signal outputted by the control signal generator, wherein the data control signals output from the second buffer are directly supplied to the data driver;
a third buffer connected between the data aligner and a data driver, wherein the third buffer receives the re-aligned data outputted from the data aligner as having a rectangular waveform and outputs the received data as having a sloped waveform in accordance with a third control signal outputted by the control signal generator, wherein the data output from the third buffer are directly supplied to the data driver;
wherein the first to third buffers are connected to the control unit;
wherein edges of the sloped waveform are formed of round shape,
wherein the gate control signals outputted by the gate control signal generator have a rectangular waveform and a first current value of 10 mA, and the control signal generator outputs the first control signal to the first buffer such that gate control signals having a sloped waveform and having a second current value of 8 mA or 6 mA are outputted to the gate driver;
wherein the data control signal outputted by the data control signal generator have a rectangular waveform and a first current value of 8 mA, and the control signal generator outputs the second control signal to the second buffer such that data control signals having a sloped waveform and having a second current value of 6 mA are outputted to the data driver;
wherein the data outputted by the data aligner have a rectangular waveform and a first current value of 12 mA, and the control signal generator outputs the third control signal to the third buffer such that data having a sloped waveform and having a second current value of 10 mA, 8 mA or 6 mA are outputted to the data driver.