IP Library Granted Patent US 8,159,073
Granted Patent B2
US 8,159,073 · App. 12/835,365 · Granted Apr 17, 2012

Interposer chip and manufacturing method thereof

Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,159,073
App. No.
12/835,365
Granted
Apr 17, 2012
Kind
B2
Abstract

The interposer chip includes a chip mounting region on which a semiconductor chip is mounted via a fixing material made of resin. The interposer chip has an insulator film, and wiring layers formed on the insulator film. At a position corresponding to a rim of the chip mounting region, a reinforcing region in which an adhesive force between the insulator film and the wiring layers are increased is provided.

Claims (69)

1. An interposer chip, comprising:

a chip mounting region on which a semiconductor chip is mounted via a fixing material made of resin;

an insulator film;

wiring layers formed on said insulator film; and

a reinforcing region provided at a position corresponding to a rim of said chip mounting region,

wherein an adhesive force between said insulator film and said wiring layers in said reinforcing region is larger than that in a surrounding region.

2. The interposer chip according to claim 1 , wherein a plurality of vias are provided in said insulator film in said reinforcing region, and said plurality of vias are filled with said wiring layers.

3. The interposer chip according to claim 2 , wherein said wiring layers comprise:

a first wiring layer filled in said plurality of vias; and

a second wiring layer provided so as to contact to said first wiring layer, and

wherein said second wiring layer is provided not to contact to said insulator film in said reinforcing region.

4. The interposer chip according to claim 3 , wherein said second wiring layer is formed on said first wiring layer in said reinforcing region.

5. The interposer chip according to claim 3 , wherein said second wiring layer is not provided in said reinforcing region and contacts to said first wiring layer at outside of said reinforcing region.

6. The interposer chip according to claim 3 , wherein said first wiring layer includes a tungsten component, and said second wiring layer includes an aluminum component.

7. The interposer chip according to claim 1 , wherein said semiconductor chip is sealed by a sealing material made of resin, and said sealing material and said fixing material are different from each other in a curing temperature.

8. A semiconductor device, comprising:

a main substrate;

a first semiconductor chip mounted on said main substrate; and

a second semiconductor chip mounted on said main substrate via an interposer chip,

wherein said interposer chip comprises:

a chip mounting region on which said second semiconductor chip is mounted via a fixing material made of resin;

an insulator film;

wiring layers formed on said insulator film; and

a reinforcing region provided at a position corresponding to a rim of said chip mounting region, and

wherein an adhesive force between said insulator film and said wiring layers in said reinforcing region is larger than that in a surrounding region.

9. A method of manufacturing an interposer chip, said inter poser chip having a chip mounting region and mounting a semiconductor chip on said chip mounting region via a fixing material made of resin, comprising:

forming an insulator film;

forming wiring layers on said insulator film; and

forming reinforcing region at a position corresponding to a rim of said chip mounting region,

wherein said reinforcing region is a region in which an adhesive force between said insulator film and said wiring layers is larger than that in a surrounding region.

10. The method of manufacturing the interposer chip according to claim 9 , wherein said forming wiring layers comprises:

forming a plurality of vias in said insulator film; and

depositing said wiring layers so as to fill said plurality of vias.

11. The method of manufacturing the interposer chip according to claim 10 , wherein said depositing said wiring layers comprises:

forming a first wiring layer so as to fill said plurality of vias; and

forming a second wiring layer so as to contact to said first wiring layer and not to contact to said insulator film in said reinforcing region.

12. The method of manufacturing the interposer chip according to claim 11 , wherein said forming said first wiring layer comprises:

depositing said first wiring layer on a whole surface of said insulator film; and

etching said deposited first wiring layer to have a predetermined shape, and

wherein said forming said second wiring layer comprises:

depositing said second wiring layer on said whole surface of said insulator film after said etching said deposited first wiring layer; and

etching said deposited second wiring layer to have a predetermined shape.

13. The method of manufacturing the interposer chip according to claim 12 , wherein said etching said second wiring layer comprises, etching said second wiring layer such that said second wiring layer remains on said first wiring layer.

14. The method of manufacturing the interposer chip according to claim 12 , wherein said etching said second wiring layer comprises, etching said second wiring layer such that said second wiring layer are removed from said reinforcing region and contacts to said first wiring layer at an outside of said reinforcing region.

15. The method of manufacturing the interposer chip according to claim 14 , wherein said etching said first wiring layer and said etching said second wiring layer are carried out in one process.

16. The method of manufacturing the interposer chip according to claim 11 , wherein said first wiring layer comprises a tungsten component, and said second wiring layer comprises an aluminum component.

17. A manufacturing method of a semiconductor device, comprising:

mounting a semiconductor chip on an interposer chip via a fixing material made of resin;

curing said fixing material by heat after said mounting;

sealing said semiconductor chip by a sealing material made of resin after said curing said fixing material; and

curing said sealing material by heat,

wherein said interposer chip comprises:

a chip mounting region on which said semiconductor chip is mounted;

an insulator film;

wiring layers formed on said insulator film; and

a reinforcing region provided at a position corresponding to a rim of said chip mounting region,

wherein an adhesive force between said insulator film and said wiring layers in said reinforcing region is larger than that in a surrounding region, and

wherein a curing temperature of said fixing material and a curing temperature of said sealing material are different from each other.

18. A manufacturing method of a semiconductor device, comprising:

preparing a main substrate;

mounting a first semiconductor chip on said main substrate; and

mounting a second semiconductor chip on said main substrate via an interposer chip,

wherein said interposer chip comprises:

a chip mounting region on which a semiconductor chip is mounted via a fixing material made of resin;

an insulator film;

wiring layers formed on said insulator film; and

a reinforcing region provided at a position corresponding to a rim of said chip mounting region,

wherein an adhesive force between said insulator film and said wiring layers in said reinforcing region is larger than that in a surrounding region, and

wherein a curing temperature of said fixing material and a curing temperature of said sealing material are different from each other.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2010
From: TOGAWA, RYUICHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024684/0313 →
Priority Claims (1)
JP 2009-190421 · Aug 19, 2009 · national
Continuity (1)
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