Semiconductor storage device

1. A semiconductor storage device comprising:

a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; and

a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to a selected memory cell through a selected first wiring and a selected second wiring,

when applying the control voltage to the memory cell plural times, the control circuit operative to set a value of the control voltage applied in a first control voltage application operation to be substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element in the memory cell from the high resistance state to the low resistance state, and

the control circuit operative to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value in each of second and subsequent control voltage application operations.

2. The semiconductor storage device according to claim 1 ,

wherein the certain value is a difference between a minimum value of the distribution of the voltage value of one memory cell in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the high resistance state to the low resistance state and a maximum value of the distribution of the voltage value of one memory cell required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state.

3. The semiconductor storage device according to claim 1 ,

wherein the control circuit reads the state of the selected memory cell during each of the plurality of control voltage application operations, and

the control circuit controls the application of the control voltage to the first wirings and the second wirings based on the state of the selected memory cell.

4. The semiconductor storage device according to claim 1 ,

wherein, when a transition of the resistance state of the memory cell from the low resistance state to the high resistance state is detected by a read operation, the control circuit stops the application of the control voltage to the first wiring and the second wiring corresponding to the memory cell.

5. The semiconductor storage device according to claim 1 ,

wherein, when the value of the control voltage reaches the maximum value of the distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state, the control circuit ends the application of the control voltage.

6. The semiconductor storage device according to claim 1 ,

wherein the control voltage includes a first control voltage applied to the first wiring and a second control voltage applied to the second wiring and lower than the first control voltage, and

the control circuit applies the first control voltage to the plurality of first wirings at the same time.

7. The semiconductor storage device according to claim 1 ,

wherein the certain value is obtained by dividing the difference between the maximum value of the distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state and the minimum value of the distribution of the voltage values of all the memory cells required to transit the resistance state of the variable resistance element of the memory cell from the high resistance state to the low resistance state by a predetermined number of times the control voltage is applied.

8. A semiconductor storage device comprising:

a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; and

a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to a selected memory cell through a selected first wiring and a selected second wiring,

when applying the control voltage to the memory cell plural times, the control circuit operative to set a value of the control voltage applied in a first control voltage application operation to be equal to or less than a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element in the memory cell from the high resistance state to the low resistance state,

the control circuit operative to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value in each of second and subsequent control voltage application operations, and

the certain value being a difference between a minimum value of the distribution of the voltage value of one memory cell in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the high resistance state to the low resistance state and a maximum value of the distribution of the voltage value of one memory cell required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state.

9. The semiconductor storage device according to claim 8 ,

wherein, when applying the control voltage to the memory cell plural times, the control circuit operative to set the value of the control voltage applied in the first control voltage application operation to be equal to or more than a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element in the memory cell from the low resistance state to the high resistance state.

10. The semiconductor storage device according to claim 8 ,

wherein the control circuit reads the state of the selected memory cell during each of the plurality of control voltage application operations, and

the control circuit controls the application of the control voltage to the first wirings and the second wirings based on the state of the selected memory cell.

11. The semiconductor storage device according to claim 8 ,

wherein, when a transition of the resistance state of the memory cell from the low resistance state to the high resistance state is detected by a read operation, the control circuit stops the application of the control voltage to the first wiring and the second wiring corresponding to the memory cell.

12. The semiconductor storage device according to claim 8 ,

wherein, when the value of the control voltage reaches the maximum value of the distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state, the control circuit ends the application of the control voltage.

13. The semiconductor storage device according to claim 8 ,

wherein the control voltage includes a first control voltage applied to the first wiring and a second control voltage applied to the second wiring and lower than the first control voltage, and

the control circuit applies the first control voltage to the plurality of first wirings at the same time.

14. The semiconductor storage device according to claim 8 ,

wherein the certain value is obtained by dividing the difference between the maximum value of the distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state and the minimum value of the distribution of the voltage values of all the memory cells required to transit the resistance state of the variable resistance element of the memory cell from the high resistance state to the low resistance state by a predetermined number of times the control voltage is applied, and

the control circuit does not operate the memory cell in which the difference between the minimum value of the distribution of the voltage value of one memory cell required to transit the resistance state of the variable resistance element from the high resistance state to the low resistance state and the maximum value of the distribution of the voltage value of one memory cell required to transit the resistance state of the variable resistance element from the low resistance state to the high resistance state is less than the certain value.

15. A semiconductor storage device comprising:

a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; and

a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to a selected memory cell through a selected first wiring and a selected second wiring,

when applying the control voltage to the memory cell plural times, the control circuit operative to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value in each control voltage application operation, and

the certain value being a difference between a minimum value of the distribution of the voltage value of one memory cell in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the high resistance state to the low resistance state and a maximum value of the distribution of the voltage value of one memory cell required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state.

16. The semiconductor storage device according to claim 15 ,

wherein the control circuit reads the state of the selected memory cell during each of the plurality of control voltage application operations, and

the control circuit controls the application of the control voltage to the first wirings and the second wirings based on the state of the selected memory cell.

17. The semiconductor storage device according to claim 15 ,

wherein, when a transition of the resistance state of the memory cell from the low resistance state to the high resistance state is detected by a read operation, the control circuit stops the application of the control voltage to the first wiring and the second wiring corresponding to the memory cell.

18. The semiconductor storage device according to claim 15 ,

wherein, when the value of the control voltage reaches the maximum value of the distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state, the control circuit ends the application of the control voltage.

19. The semiconductor storage device according to claim 15 ,

wherein the control voltage includes a first control voltage applied to the first wiring and a second control voltage applied to the second wiring and lower than the first control voltage, and

the control circuit applies the first control voltage to the plurality of first wirings at the same time.

20. The semiconductor storage device according to claim 15 ,

wherein the certain value is obtained by dividing the difference between the maximum value of the distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element of the memory cell from the low resistance state to the high resistance state and the minimum value of the distribution of the voltage values of all the memory cells required to transit the resistance state of the variable resistance element of the memory cell from the high resistance state to the low resistance state by a predetermined number of times the control voltage is applied, and

the control circuit does not operate the memory cell in which the difference between the minimum value of the distribution of the voltage value of one memory cell required to transit the resistance state of the variable resistance element from the high resistance state to the low resistance state and the maximum value of the distribution of the voltage value of one memory cell required to transit the resistance state of the variable resistance element from the low resistance state to the high resistance state is less than the certain value.