Semiconductor device and method of fabricating the same
A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.
1. A method of fabricating a semiconductor device, comprising:
forming a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric on a substrate;
performing at least one of a dry etching process and a wet etching process on a portion of the interlayer dielectric and the gate insulating layer to form a contact hole to a predetermined depth; and
wet etching the contact hole to complete the contact hole and expose a portion of the semiconductor layer,
wherein the exposed portion of the semiconductor layer is not subjected to a dry etching process.
2. The method of claim 1 , wherein the dry etching process includes any one of an ion etching process and a reactive etching process.
3. The method of claim 1 , further comprising removing a photoresist pattern before carrying out the wet etching that completes the contact hole.
4. The method of claim 1 , wherein the dry etching process includes at least one of a high etch rate dry etching process and a high selectivity dry etching process.
5. A method of fabricating a semiconductor device, comprising:
forming a thin film transistor (TFT) including a source electrode and a drain electrode on a substrate;
forming a passivation layer and a planarization layer on the TFT;
performing at least one of a dry etching process and a wet etching process on a portion of the passivation layer and the planarization layer to form a via hole to a predetermined depth; and
wet etching the via hole to complete the via hole and expose a portion of either the source electrode or the drain electrode,
wherein the exposed portion of either the source electrode or the drain electrode is not subjected to a dry etching process.
6. The method of claim 5 , wherein the dry etching process includes any one of an ion etching process and a reactive etching process.
7. The method of claim 5 , further comprising removing a photoresist pattern before carrying out the wet etching that completes the contact hole.
8. The method of claim 5 , wherein the dry etching process includes at least one of a high etch rate dry etching process and a high selectivity dry etching process.
9. A method of fabricating a semiconductor device, comprising:
forming a metal interconnection line and an interlayer dielectric on a substrate;
performing at least one of a dry etching process and a wet etching process on a portion of the interlayer dielectric to form a via hole to a predetermined depth; and
wet etching the via hole to complete the via hole and expose a portion of the metal interconnection line,
wherein the exposed portion of the metal interconnection line is not subjected to a dry etching process.
10. A method of fabricating a semiconductor device, comprising:
forming a semiconductor layer, a gate insulating layer, and a gate electrode on a substrate;
forming a planarization layer on the substrate;
performing at least one of a dry etching process and a wet etching process on a portion of the gate insulating layer and the planarization layer to form a via contact hole to a predetermined depth; and
wet etching the via contact hole to complete the via contact hole and expose a portion of the semiconductor layer,
wherein the exposed portion of the semiconductor layer is not subjected to a dry etching process.
11. A method of fabricating a semiconductor device, comprising:
forming a semiconductor layer, a gate insulating layer, and a gate electrode in a thin film transistor (TFT) region of a substrate;
forming a metal interconnection line in a metal interconnection line region spaced apart from the TFT region by a predetermined interval;
forming an interlayer dielectric in the TFT region, and forming an insulating layer in the metal interconnection line region;
performing at least one of a dry etching process and a wet etching process on a portion of the insulating layer in the metal interconnection line region, and on the interlayer dielectric and the gate insulating layer in the TFT region to form a contact hole having a predetermined depth in the TFT region and a via hole having a predetermined depth in the metal interconnection line region; and
wet etching the contact hole and the via hole to complete the contact hole and the via hole and expose a portion of the semiconductor layer in the TFT region and a portion of the metal interconnection line in the metal interconnection line region.
12. The method of claim 1 , wherein the exposed portion of the semiconductor layer has a wet-etched upper surface.
13. The method of claim 5 , wherein the exposed portion of either the source electrode or the drain electrode has a wet-etched upper surface.
14. The method of claim 9 , wherein the exposed portion of the metal interconnection line has a wet-etched upper surface.
15. The method of claim 10 , wherein the exposed portion of the semiconductor layer has a wet-etched upper surface.
16. The method of claim 11 , wherein the exposed portions of the semiconductor layer and the metal interconnection line have a wet-etched upper surface.