Adhesion and electromigration performance at an interface between a dielectric and metal
Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile capping layer. Next, an interlayer dielectric layer is formed on the compressive capping layer. Further, a first opening is formed in the ILD layer using a first chemistry. A second opening is formed in the tensile capping layer and the compressive capping layer using a second chemistry. Next, a second conductive layer is formed in the first opening and the second opening.
1. A method, comprising:
forming a bi-layer over a copper conductive layer in a first interlayer dielectric (ILD) layer on a substrate, wherein the bi-layer comprises a compressive silicon carbide nitride layer on a tensile silicon nitride layer having a tensile stress in the range of 50 Megapascals to 900 Megapascals, wherein the compressive silicon carbide nitride layer is configured to compensate for the tensile silicon nitride layer, and wherein the tensile silicon nitride layer is deposited onto the copper conductive layer and the first ILD layer, wherein the copper conductive layer is deposited in the first ILD layer on the substrate to form one or more conductive lines; and
forming a second interlayer dielectric (ILD) layer on the compressive silicon carbide nitride layer, wherein the bi-layer comprising the compressive silicon carbide nitride layer on the tensile silicon nitride layer adds the tensile stress at the copper conductive layer and increases adhesion between the copper conductive layer, the first ILD layer and the second ILD layer and is capable of being an etch stop layer.
2. The method of claim 1 , further comprising:
forming a first opening in the second ILD layer using a first chemistry; and
forming a second opening in the tensile silicon nitride layer and the compressive silicon carbide nitride layer using a second chemistry.
3. The method of claim 1 , wherein the forming the tensile silicon nitride layer includes using a plasma enhanced chemical vapor deposition having a first RF frequency.
4. The method of claim 1 , wherein the forming the compressive silicon carbide nitride layer includes using a plasma enhanced chemical vapor deposition having a second RF frequency.
5. A method to fabricate an interconnect, comprising:
depositing a tensile/compressive capping bi-layer on a first copper conductive layer in a first interlayer dielectric (ILD) layer on a substrate, wherein the depositing the bi-layer includes
depositing a tensile silicon nitride layer having a tensile stress in the range of 50 Megapascals to 900 Megapascals on the first copper conductive layer and the first ILD layer; and
depositing a compressive silicon carbide nitride layer on the tensile silicon nitride layer to compensate for the tensile silicon nitride layer;
depositing a second interlayer dielectric (ILD) layer on the bi-layer, wherein the bi-layer comprising the compressive silicon carbide nitride on the tensile silicon nitride adds the tensile stress at the first copper conductive layer and increases adhesion between the first copper conductive layer, the first ILD layer, and the second ILD layer; and
selectively etching the second ILD layer down to the bi-layer to form a first opening, wherein the bi-layer acts as an etch stop layer.
6. The method of claim 5 , wherein the tensile silicon nitride layer and the compressive silicon carbide nitride layer are deposited using a plasma enhanced chemical vapor deposition.
7. The method of claim 5 , further comprising
etching the bi-layer down to the first copper conductive layer through the first opening; and
depositing a second conductive layer in the first opening.
8. The method of claim 5 , further comprising
etching the second ILD layer to form a second opening;
etching a portion of the bi-layer exposed through the first opening down to the first copper conductive layer;
depositing a base layer in the first opening and the second opening; and
depositing a conductive material onto the base layer.
9. An apparatus, comprising:
a bi-layer over a first copper conductive layer in a first interlayer dielectric (ILD) layer on a substrate, wherein the first copper conductive layer is deposited in the first ILD layer on the substrate to form one or more conductive lines, and wherein the bi-layer comprises a compressive silicon carbide nitride layer on a tensile silicon nitride layer having a tensile stress in the range of 50 Megapascals to 900 Megapascals, wherein the compressive silicon carbide nitride layer is configured to compensate for the tensile silicon nitride layer, and wherein the tensile silicon nitride layer is deposited onto the copper conductive layer and the first ILD layer on the substrate; and
a second interlayer dielectric (ILD) layer on the compressive silicon carbide nitride layer, wherein the bi-layer adds the tensile stress at the first copper conductive layer and increases adhesion between the first copper conductive layer, the first ILD layer, and the second ILD layer and is capable of being an etch stop layer.
10. The apparatus of claim 9 , further comprising an interconnect structure in the first ILD layer to connect to the first conductive layer.
11. The apparatus of claim 9 , wherein the tensile silicon nitride layer has a thickness in the range from 25 Angstroms to 100 Angstroms.
12. The apparatus of claim 9 , wherein the compressive silicon carbide nitride layer has a thickness in the range from 100 Angstroms to 2000 Angstroms.
13. The apparatus of claim 9 , wherein the the compressive layer has a compressive stress in the range from 50 Megapascals to 1 Gigapascal.
14. A method, comprising:
forming a compressive silicon carbide nitride layer on a tensile silicon nitride layer having a tensile stress in the range of 50 Megapascals to 900 Megapascals, wherein the tensile silicon nitride layer is deposited onto a copper conductive layer in a first interlayer dielectric (ILD) layer on a substrate, wherein the compressive silicon carbide nitride layer is configured to compensate for the tensile silicon nitride layer, and wherein the copper conductive layer is deposited in the first ILD layer on the substrate to form one or more conductive lines; and
forming a second interlayer dielectric (ILD) layer on the compressive silicon carbide nitride layer, wherein the compressive silicon carbide nitride layer on the tensile silicon nitride layer adds the tensile stress at the copper conductive layer and increases adhesion between the copper conductive layer, the first ILD layer, and the second ILD layer and is capable of being an etch stop layer.