IP Library Granted Patent US 8,178,917
Granted Patent B2
US 8,178,917 · App. 12/408,249 · Granted May 15, 2012

Non-volatile semiconductor storage device having memory cells disposed three-dimensionally, and method of manufacturing the same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,178,917
App. No.
12/408,249
Granted
May 15, 2012
Kind
B2
Abstract

A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction. The second layer includes: a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and a second insulation layer formed on an upper layer of the plurality of second conductive layers. Respective ends of the second conductive layers are formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.

Claims (77)

1. A non-volatile semiconductor storage device comprising:

a first layer provided on a substrate, and functioning as a plurality of electrically rewritable memory cells connected in series; and

a second layer provided on the substrate around the first layer, and separately-placed from the first layer along a direction parallel to the substrate,

the first layer comprising:

a plurality of first conductive layers extending parallel to a substrate and laminated in a direction perpendicular to the substrate, the first conductive layers functioning as control gates of the memory cells;

a first insulation layer formed on an upper layer of the plurality of first conductive layers;

a first semiconductor layer formed to penetrate the plurality of first conductive layers; and

a charge accumulation layer formed between the first conductive layers and the first semiconductor layer and configured to be able to accumulate charges,

respective ends of the first conductive layers being formed in a stepwise manner in relation to each other in a first direction,

the second layer comprising:

a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and

a second insulation layer formed on an upper layer of the plurality of second conductive layers, and

respective ends of the second conductive layers being formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.

2. The non-volatile semiconductor storage device according to claim 1 , wherein

the first insulation layer is continuously formed over the plurality of first conductive layers, and

the second insulation layer is continuously formed over the plurality of second conductive layers.

3. The non-volatile semiconductor storage device according to claim 1 , wherein

the second layer further comprises:

a connecting conductive layer extending from an upper layer to a lower layer of the second layer; and

an interlayer insulation layer surrounding the side surfaces of the connecting conductive layer, and

the predetermined area is configured to be filled up with the connecting conductive layer and the interlayer insulation layer.

4. The non-volatile semiconductor storage device according to claim 3 , wherein

the second insulation layer is continuously formed on the top surface of the interlayer insulation layer.

5. The non-volatile semiconductor storage device according to claim 1 , wherein

the second layer further comprises:

a connecting conductive layer extending from an upper layer to a lower layer of the second layer; and

an interlayer insulation layer surrounding the side surfaces of the connecting conductive layer,

the second insulation layer is continuously formed on the side surfaces of respective ends of the plurality of conductive layers, and

the predetermined area is configured to be filled up with the connecting conductive layer, the interlayer insulation layer, and the second conductive layers.

6. The non-volatile semiconductor storage device according to claim 1 , wherein

the second layer further comprises a connecting conductive layer extending from an upper layer to a lower layer of the second layer,

the second insulation layer is continuously formed on the side surfaces of respective ends of the plurality of conductive layers, and

the predetermined area is configured to be filled up with the connecting conductive layer and the second conductive layers.

7. The non-volatile semiconductor storage device according to claim 1 , further comprising a third layer formed on a lower layer of the first layer and functioning as a selection transistor connected to one ends of the memory cells, wherein

the third layer comprises:

a third conductive layer located at a lower layer of the plurality of first conductive layers and extending in parallel to the substrate, the third conductive layer functioning as a control gate of the selection transistor;

a second semiconductor layer formed to penetrate the third conductive layer and in contact with the bottom surface of the first semiconductor layer; and

a first gate insulation layer formed between the third conductive layer and the second semiconductor layer.

8. The non-volatile semiconductor storage device according to claim 1 , further comprising a fourth layer formed on an upper layer of the first layer and functioning as a selection transistor connected to the other ends of the memory cells, wherein

the fourth layer comprises:

a fourth conductive layer located at an upper layer of the plurality of first conductive layers and extending in parallel to the substrate, the fourth conductive layer functioning as a control gate of the selection transistor;

a third semiconductor layer formed to penetrate the fourth conductive layer and in contact with the top surface of the first semiconductor layer; and

a second gate insulation layer formed between the fourth conductive layer and the third semiconductor layer.

9. The non-volatile semiconductor storage device according to claim 1 , wherein

the first insulation layer and the second insulation layer are composed of silicon nitride.

10. The non-volatile semiconductor storage device according to claim 1 , further comprising a fifth layer formed on a lower layer of the second layer and functioning as a MOS transistor, wherein

the fifth layer comprises:

a connecting conductive layer extending from the second layer to a lower layer; and

a fifth conductive layer in contact with the bottom surface of the connecting conductive layer and extending parallel to the substrate, the fifth conductive layer functioning as a control gate of the MOS transistor.

11. The non-volatile semiconductor storage device according to claim 1 , wherein those ends of the plurality of second conductive layers adjacent to the first layer in the first direction are formed in a stepwise manner in relation to each other.

12. A method of manufacturing a non-volatile semiconductor storage device including: a first area provided on a substrate, and functioning as a plurality of electrically rewritable memory cells connected in series; and a second area provided on the substrate around the first area, and separately-placed from the first area along a direction parallel to the substrate,

the method comprising:

forming a plurality of first conductive layers extending parallel to the substrate so that the first conductive layers are laminated on the substrate over multiple layers;

processing the plurality of first conductive layers in a stepwise manner in relation to each other at respective ends in a first direction in the first area;

forming a first through hole to penetrate the plurality of first conductive layers at a predetermined area in the second area;

forming a first insulation layer in the first through hole;

forming a second through hole to penetrate the first insulation layer; and

forming second conductive layers to fill up the second through hole.

13. The method of manufacturing the non-volatile semiconductor storage device according to claim 12 , the method further comprising:

continuously forming a second insulation layer to cover the plurality of first conductive layers.

14. The method of manufacturing the non-volatile semiconductor storage device according to claim 13 , wherein

after the plurality of first conductive layers are processed in a stepwise manner in relation to each other and before the first through hole is formed, the second insulation layer is continuously formed to cover the plurality of first conductive layers, and

the first through hole is formed to penetrate the plurality of first conductive layers and the second insulation layer.

15. The method of manufacturing the non-volatile semiconductor storage device according to claim 13 , wherein

after the first through hole is formed and the plurality of first conductive layers are processed in a stepwise manner in relation to each other, and before the first insulation layer is formed in the first through hole, the second insulation layer is continuously formed to cover the plurality of first conductive layers.

16. The method of manufacturing the non-volatile semiconductor storage device according to claim 13 , wherein

after the first insulation layer is formed in the first through hole and the plurality of first conductive layers are processed in a stepwise manner in relation to each other, the second insulation layer is continuously formed to cover the plurality of first conductive layers.

17. The method of manufacturing the non-volatile semiconductor storage device according to claim 12 , wherein

a resist is formed on an upper layer of the plurality of first conductive layers, the resist is repeatedly slimed down and the first conductive layers are repeatedly etched using the resist as a mask to process the first conductive layers in a stepwise manner in relation to each other.

18. The method of manufacturing the non-volatile semiconductor storage device according to claim 13 , wherein

the second insulation layer is composed of silicon nitride.

19. The method of manufacturing the non-volatile semiconductor storage device according to claim 12 , wherein

the first insulation layer is composed of material with a higher etching rate than silicon oxide.

20. The method of manufacturing the non-volatile semiconductor storage device according to claim 12 , the method further comprising:

forming a third conductive layer extending in parallel to the substrate before forming the plurality of first conductive layers, wherein

the plurality of first conductive layers are formed on an upper layer of the third conductive layer, and

the second conductive layers are formed in contact with the top surface of the third conductive layer.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2009
From: TANAKA, HIROYASU; KATSUMATA, RYOTA; KITO, MASARU; FUKUZUMI, YOSHIAKI; KIDOH, MASARU; KOMORI, YOSUKE; AOCHI, HIDEAKI; ISHIDUKI, MEGUMI; MATSUOKA, YASUYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 022443/0446 →
Priority Claims (1)
JP 2008-117508 · Apr 28, 2008 · national
Continuity (1)
Related Publication 20090267135A1 · Oct 29, 2009