Parametric data-based process monitoring for adaptive body bias control

1. A system for providing adaptive body bias control, the system comprising:

a chip comprising at least one critical path and a module comprising one or more transistors, a parametric process monitor for sensing information associated with the transistors, and a voltage regulator for regulating a bulk node voltage associated with the transistors;

a memory device storing critical path data associated with the at least one critical path on the chip and parametric data associated with the chip; and

a microcontroller in communication with the chip and the memory device, the microcontroller comprising an adaptive body biasing control module configured to:

receive monitored data associated with the transistors from the parametric process monitor;

receive from the voltage regulator a proposed adjustment to a bulk node voltage corresponding to the module;

based on the proposed adjustment and the parametric data stored in the memory device, determine an estimated gate delay;

estimate a critical path delay, based on the gate delay; and

if the estimated critical path delay does not exceed a maximum delay corresponding to the critical path data, instruct the voltage regulator to adjust a bulk node voltage.

2. The system of claim 1 , wherein the memory device comprises on-chip memory.

3. The system of claim 1 , wherein the microcontroller and the memory device are located on the chip.

4. The system of claim 1 , wherein the parametric data comprises simulation data of a gate delay of each gate type in the chip design at a plurality of voltage and temperature conditions and saturation currents.

5. The system of claim 1 , wherein the critical path data comprises a simulation of a critical path replica in the chip according to predetermined voltage and temperature conditions.

6. The system of claim 1 , wherein the critical path data comprises data from a static timing analysis of the chip.

7. The system of claim 1 , wherein the memory device is configured to update the critical path data and the parametric data.

8. A method for adaptive body bias control, the method comprising:

modeling parametric data associated with a chip design;

modeling critical path data associated with the chip design;

providing a chip according to the chip design;

storing the parametric data and the critical path data in a memory on the chip;

reading data from a parametric sensor on the chip;

based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and

adjusting the bulk node voltage according to the optimized bulk node voltage, wherein the modeling the parametric data comprises simulating a gate delay of each gate type in the chip design at a plurality of voltage and temperature conditions and saturation currents.

9. The method of claim 8 , wherein the modeling the critical path data comprises simulating a critical path replica according to predetermined voltage and temperature conditions.

10. The method of claim 8 , wherein the parametric sensor comprises an on-die sensor.

11. The method of claim 10 , wherein the on-die sensor comprises at least one of a ring oscillator and a thermometer.

12. The method of claim 8 , wherein the reading data from a parametric sensor on the chip comprises receiving saturation current information.

13. The method of claim 12 , wherein the saturation current information comprises the saturated on current of a transistor on the chip.

14. The method of claim 8 , wherein the determining the optimized bulk node voltage comprises estimating a delay associated with a critical path in the chip as function of one or more of a saturation current, a stack height, voltage, temperature, and wire delay.

15. The method of claim 8 , wherein the determining the optimized bulk node voltage comprises:

receiving an adjustment voltage level from a voltage regulator on the chip;

determining an estimated gate delay based on the adjustment voltage level; and

determining a critical path delay based on the estimated gate delay.

16. The method of claim 15 , wherein the bulk node voltage is adjusted if the critical path delay exceeds a maximum delay associated with the chip.

17. The method of claim 8 , further comprising updating at least one of the critical path data and the parametric data stored in the memory.

18. A method for adaptive body bias control, the method comprising:

modeling parametric data associated with a chip design;

modeling critical path data associated with the chip design;

providing a chip according to the chip design;

storing the parametric data and the critical path data in a memory on the chip;

reading data from a parametric sensor on the chip;

based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and

adjusting the bulk node voltage according to the optimized bulk node voltage, wherein the modeling the parametric data comprises simulating, for each gate type in the chip design, the saturation current and bulk node voltage as a function of voltage and temperature conditions.

19. The method of claim 18 , wherein the critical path data comprises data from a static timing analysis of the chip.

20. A computer program embodied in a non-transitory computer-readable medium and executable by a processor, the computer program comprising logic configured to:

receive monitored data associated with transistors on a chip from a parametric process monitor;

receive a proposed voltage adjustment to a bulk node voltage corresponding to the chip;

based on the proposed adjustment and parametric data stored in a memory device, determine an estimated gate delay, wherein the parametric data comprises a simulation of a gate delay of each gate type on the chip at a plurality of voltage and temperature conditions and saturation currents;

estimate a critical path delay, based on the gate delay; and

if the estimated critical path delay does not exceed a maximum delay corresponding to critical path data stored in the memory device, instruct a voltage regulator to adjust a bulk node voltage.

21. The computer program of claim 20 , wherein the processor comprises a microcontroller.