Array substrate for liquid crystal display device and method of fabricating the same
An array substrate for an LCD device includes a first TFT including a first semiconductor layer, a first gate electrode, wherein the first gate electrode is directly over the first semiconductor layer; a first protrusion extending from the first gate electrode along an edge of the first semiconductor layer; a second TFT including a second semiconductor layer, a second gate electrode, wherein the second gate electrode is directly over the second semiconductor layer; a second protrusion extending from the second gate electrode along an edge of the second semiconductor layer; a third TFT connected to crossed data and gate lines including a third semiconductor layer, a third gate electrode, wherein the third gate electrode is directly over the third semiconductor layer; a third protrusion extending from the third gate electrode along an edge of the third semiconductor layer; and a pixel electrode.
1. A TFT for an LCD device, comprising:
a semiconductor layer;
a gate insulating layer on the semiconductor layer;
a gate electrode directly over the semiconductor layer on the gate insulating layer;
first to fourth protrusions extending from the gate electrode along an edge of the semiconductor layer;
an interlayer insulating layer on the gate electrode, the interlayer insulating layer having first and second contact holes exposing the semiconductor layer; and
a source electrode and a drain electrode spaced apart from the source electrode on the interlayer insulating layer, the source and drain electrodes connected to the semiconductor layer through the first and second contact holes, respectively,
wherein the gate electrode has first and second sides opposite to each other, and wherein the first and second protrusions are disposed at the first side, and the third and fourth protrusions are disposed at the second side,
wherein the first and second protrusions are disposed at two crossing portions of the gate electrode and the semiconductor layer, respectively, and spaced apart from each other, and the third and fourth protrusions are disposed at the other two crossing portions of the gate electrode and the semiconductor layer, respectively, and spaced apart from each other,
wherein the first and second protrusions protrude toward the source electrode, and the third and fourth protrusions protrude toward the drain electrode,
wherein each of the first to fourth protrusions has a triangle shape at a crossing point of the gate electrode and the semiconductor layer.
2. The TFT according to claim 1 , wherein the semiconductor layer includes an active region, an LDD region and an ohmic contact region, the LDD region is disposed at both sides of the active region and the ohmic contact region is disposed at outer sides of the LDD region.
3. The TFT according to claim 2 , wherein the ohmic contact region is doped with high concentration impurities, and the LDD region is doped with low concentration impurities.
4. The TFT according to claim 1 , wherein the semiconductor layer includes an active region and an ohmic contact region at both sides of the active region.
5. The TFT according to claim 4 , wherein the ohmic contact region is doped with one of p-type impurities and n-type impurities.
6. The TFT according to claim 1 , wherein the semiconductor layer is made of polycrystalline silicon.