Single stage inverter device, and related controlling method, for converters of power from energy sources, in particular photovoltaic sources

1. A single stage inverter device, for converters of power from dc energy sources to an electric ac network or grid having at least one phase, of pulsation frequency ω grid , comprising switching means capable to periodically connect, with period T s lower than the period T grid corresponding to the pulsation frequency ω grid , a source, capable to output a voltage v g (t) of average value V g , to the grid so that the device output current i 0 (t) is in phase with the voltage v 0 (t) of at least one phase of the grid, the maximum value of which is V o,max , the switching means being controlled by controlling electronic means operating according to a control over a single switching cycle of the switching means, the device seeing an output inductance L, the device comprising a sensing resistor of resistance R s connected in series to the grid, the controlling electronic means comprising:

a resettable integrator circuit having a time constant τ such that τ<T s , the input of which receives a voltage signal (V c −K g *V g ) equal to the difference between a control voltage V c and a voltage proportional by a first factor K g to the output voltage v g (t) of the source,

comparator means, capable to output a signal indicative of the comparison of a voltage drop [R s ·i o (t)] on the sensing resistor with the sum of the output signal of the integrator circuit and a voltage [K·v o (t)] proportional by a second factor K to the voltage v 0 (t) of the grid, and

generator means capable to receive the output signal from the comparator means and a signal indicative of the phase of the grid for providing one or more signals for controlling the switching means,

the control voltage V c and the first factor K g being such as to fulfil the following first constraint:

V

c

≥

K

g

⁢

V

g

+

(

2

⁢

⁢

V

o

,

max

-

V

g

)

⁢

R

s

⁢

τ

2

⁢

⁢

L

,

wherein the device fulfils a second constraint whereby the input signal of the integrator circuit is always positive, and it fulfils a third constraint whereby, at any time instant, the input voltage of the switching means is higher than the output voltage thereof, and it fulfils a fourth constraint whereby

K

⁡

(

1

-

P

o

⁡

(

S

)

α

·

P

g

,

MPP

⁡

(

S

max

)

)

·

(

1

-

γ

)

≤

V

m

V

g

⁢

❘

min

⁢

≤

V

m

V

g

⁢

❘

max

⁢

⁢

V

m

V

g

⁢

❘

min

⁢

≤

V

m

V

g

⁢

❘

max

⁢

≤

K

⁡

(

1

-

P

o

⁡

(

S

)

α

·

P

g

,

MPP

⁡

(

S

max

)

)

·

(

1

+

γ

)

where:

v

m

=

(

V

c

-

K

g

·

v

g

τ

)

·

T

s

P o (S) is the device output average power for a set S of operation conditions,

P g,MPP (S max ) is the maximum power deliverable by the source,

α is a first coefficient of overload, with α≧1, and

γ is a second coefficient, with γ<1.

2. A device according to claim 1 , wherein the control voltage V c and the first factor K g are such that:

V c >K g ( V g +ΔV g )

where ΔV g is the peak-to-peak amplitude of the oscillation of the voltage v g (t).

3. A device according to claim 1 , wherein the second factor K is such that:

V g −ΔV g >(1 +K )· V o,max

where ΔV g is the peak-to-peak amplitude of the oscillation of the voltage v g (t).

4. A device according to claim 1 , wherein the resettable integrator circuit is reset when |R s *i o |>|K*v o |−v m *t/T s .

5. A device according to claim 1 , wherein the controlling electronic means further comprises processing electronic means, connected at its input to the source for determining the power thereof with sampling period T a , capable to output at least one signal capable to vary the value of at least one corresponding parameter, selected from the group comprising the resistance R s , the time constant τ, the control voltage V c , the first factor K g , the second factor K, and a combination of them, by continuously perturbing the output average power P o (S) so as to search the maximum output power point according to the so called hill climbing method.

6. A device according to claim 5 , wherein the processing electronic means is capable to detect the instant output voltage and current of the source.

7. A device according to claim 5 , wherein T a >T s .

8. A device according to claim 5 , wherein the processing electronic means outputs the control voltage V c , that is provided as input to the integrator circuit.

9. A device according to claim 1 , wherein the controlling electronic means are at least partially integrated in at least one microprocessor and/or at least one digital signal processor and/or at least one microcontroller.

10. A device according to claim 1 , wherein the source is such that the point of maximum input power of the device is variable and/or the factor of output power or PF-out of the device is variable with the set S of operation conditions.

11. A device according to claim 10 , wherein the source is a renewable energy source.

12. A device according to claim 11 , wherein the source is a photovoltaic source, the operation conditions of the set S being one or more conditions selected from the group comprising sunlight level, temperature, and source degradation.

13. A device according to claim 1 , wherein the electric network is a single-phase or three-phase network.

14. A single switching cycle method of controlling switching means of a single stage inverter device, for converters of power from dc energy sources to an electric ac network or grid having at least one phase, of pulsation frequency ω grid , wherein the switching means periodically connects, with period T s lower than the period T grid corresponding to the pulsation frequency ω grid , a source, capable to output a voltage v g (t) of average value V g , to the grid so that the device output current i 0 (t) of each phase is in phase with the voltage v 0 (t) of the same phase of the grid the maximum value of which is V o,max , the method comprising the following steps:

A. integrating, according to a time constant τ such that τ<T s , a voltage signal (V c −K g *v g ) equal to the difference between a control voltage V c and a voltage proportional by a first factor K g to the output voltage v g (t) of the source,

B. comparing a voltage drop [R s ·i o (t)], on a sensing resistor of resistance R s connected in series to the grid, with the sum of the result of the integration of step A with a voltage [K·v o (t)] proportional by a second factor K to the voltage v 0 (t) of the grid, and

C. generating one or more signals for controlling the switching means on the basis of the result of the comparison of step B,

the control voltage V c and the first factor K g being such as to fulfil the following first constraint:

V

c

≥

K

g

⁢

V

g

+

(

2

⁢

⁢

V

o

,

max

-

V

g

)

⁢

R

s

⁢

τ

2

⁢

⁢

L

,

where L is the output inductance seen by the inverter device, wherein the voltage signal integrated in step A is always positive, the input voltage of the switching means (M 1 -M 4 ) is higher than the output voltage thereof, and

K

⁡

(

1

-

P

o

⁡

(

S

)

α

·

P

g

,

MPP

⁡

(

S

max

)

)

·

(

1

-

γ

)

≤

V

m

V

g

⁢

❘

min

⁢

≤

V

m

V

g

⁢

❘

max

⁢

⁢

V

m

V

g

⁢

❘

min

⁢

≤

V

m

V

g

⁢

❘

max

⁢

≤

K

⁡

(

1

-

P

o

⁡

(

S

)

α

·

P

g

,

MPP

⁡

(

S

max

)

)

·

(

1

+

γ

)

where:

v

m

=

(

V

c

-

K

g

·

v

g

τ

)

·

T

s

P o (S) is the device output average power for a set S of operation conditions,

P g,MPP (S max ) is the maximum power deliverable by the source,

α is a first coefficient of overload, with a α≧1, and

γ is a second coefficient, with γ<1.

15. A method according to claim 14 , wherein the control voltage V c and the first factor K g are such that:

V c >K g ( V g +ΔV g )

where ΔV g is the peak-to-peak amplitude of the oscillation of the voltage v g (t).

16. A method according to claim 14 , wherein the second factor K is such that:

V g −ΔV g >(1 +K )· V o,max

where ΔV g is the peak-to-peak amplitude of the oscillation of the voltage v g (t).

17. A method according to claim 14 , wherein the result of the integration of step A is reset when

| R s *i o |>|K*v o |−v m *t/T s .

18. A method of scaling a single stage inverter device, for converters of power from dc energy sources to an electric ac network or grid having at least one phase, of pulsation frequency ω grid , wherein the device comprises switching means capable to periodically connect, with period T s lower than the period T grid corresponding to the pulsation frequency ω grid , a source, capable to output a voltage v g (t) of average value V g , to the grid so that the device output current i 0 (t) is in phase with the voltage v 0 (t) of at least one phase of the grid, the maximum value of which is V o,max , the switching means being controlled by controlling electronic means operating according to a control over a single switching cycle of the switching means, the device seeing an output inductance L, the device comprising a sensing resistor of resistance R s connected in series to the grid, the controlling electronic means comprising:

a resettable integrator circuit having a time constant τ such that τ<T s , the input of which receives a voltage signal (V c −K g *v g ) equal to the difference between a control voltage V c and a voltage proportional by a first factor K g to the output voltage v g (t) of the source,

comparator means, capable to output a signal indicative of the comparison of a voltage drop [R s ·i o (t)] on the sensing resistor with the sum of the output signal of the integrator circuit and a voltage [K·v o (t)] proportional by a second factor K to the voltage v 0 (t) of the grid, and

generator means capable to receive the output signal from the comparator means and a signal indicative of the phase of the grid for providing one or more signals for controlling the switching means,

the control voltage V c and the first factor K g being such as to fulfil the following first constraint:

V

c

≥

K

g

⁢

V

g

+

(

2

⁢

⁢

V

o

,

max

-

V

g

)

⁢

R

s

⁢

τ

2

⁢

⁢

L

,

wherein the device fulfils a second constraint whereby the input signal of the integrator circuit is always positive, and it fulfils a third constraint whereby, at any time instant, the input voltage of the switching means is higher than the output voltage thereof, and it fulfils a fourth constraint whereby

K

⁡

(

1

-

P

o

⁡

(

S

)

α

·

P

g

,

MPP

⁡

(

S

max

)

)

·

(

1

-

γ

)

≤

V

m

V

g

⁢

❘

min

⁢

≤

V

m

V

g

⁢

❘

max

⁢

⁢

V

m

V

g

⁢

❘

min

⁢

≤

V

m

V

g

⁢

❘

max

⁢

≤

K

⁡

(

1

-

P

o

⁡

(

S

)

α

·

P

g

,

MPP

⁡

(

S

max

)

)

·

(

1

+

γ

)

where:

v

m

=

(

V

c

-

K

g

·

v

g

τ

)

·

T

s

P o (S) is the device output average power for a set S of operation conditions,

P g,MPP (S max ) is the maximum power deliverable by the source,

α is a first coefficient of overload, with α≧1, and

γ is a second coefficient, with γ<1,

wherein the scaling method selects the values of the resistance R s , of the time constant τ, of the control voltage V C , of the first factor K g , and of the second factor K such as to minimise at least one merit figure selected from the group comprising:

a merit figure Ψ 0 , equal to

Ψ 0 =P g,MPP ( S 0 )− P o ( S 0 )

where S 0 is a set S of specific operation conditions and P g (S 0 ) is the power delivered by the source in correspondence of the set S 0 of specific operation conditions, and

a further merit figure Ψ 3 , equal to the root mean square deviation of the maximum power P g,MPP (S) deliverable by the source and the device output power P o (S) over a whole range [S min , S max ] of sets S of operation conditions, that is

Ψ

3

=

∑

k

=

1

N

⁢

⁢

[

P

g

,

MPP

⁡

(

S

k

)

-

P

o

⁡

(

S

k

)

]

2

P

g

,

MPP

2

⁡

(

S

k

)

where S min and S max are sets of specific operation conditions whereby P g,MPP (S) assumes, respectively, the minimum and the maximum value within the range [S min , S max ].

19. A method according to claim 18 , wherein the merit figure Ψ 0 =Ψ 1 is calculated for the set S min of specific operation conditions.

20. A method according to claim 18 , wherein the merit figure Ψ 0 =Ψ 2 is calculated for the set S max of specific operation conditions.

21. A method according to claim 18 , wherein the values of the resistance R s , of the time constant τ, of the control voltage V c , of the first factor K g , and of the second factor K are determined through at least one either deterministic and stochastic numerical technique.

22. A method according to claim 21 , characterised in that said at least one either deterministic and stochastic numerical technique comprises an estimation through the Montecarlo method and/or an evolutionary type search algorithms, preferably a genetic algorithm.

23. A method according to claim 18 , wherein the source is a photovoltaic source, the operation conditions of the set S being one or more conditions selected from the group comprising sunlight level, temperature, and source degradation.

24. A controller device for controlling switching means of a single stage inverter device, for converters of power from dc energy sources to an electric ac network or grid having at least one phase, of pulsation frequency ω grid , wherein the switching means are capable to periodically connect, with period T s lower than the period T grid corresponding to the pulsation frequency ω grid , a source, capable to output a voltage v g (t) of average value V g , to the grid so that the device output current i 0 (t) is in phase with the voltage v 0 (t) of at least one phase of the grid, the maximum value of which is V o,max , wherein the controller device operates according to a control over a single switching cycle of the switching means, wherein the device sees an output inductance L, wherein the device comprises a sensing resistor of resistance R s connected in series to the grid, wherein the controller device comprises:

a resettable integrator circuit having a time constant τ such that τ<T s , the input of which receives a voltage signal (V c −K g *v g ) equal to the difference between a control voltage V c and a voltage proportional by a first factor K g to the output voltage v g (t) of the source,

comparator means, capable to output a signal indicative of the comparison of a voltage drop [R s ·i o (t)] on the sensing resistor with the sum of the output signal of the integrator circuit and a voltage [K·v o (t)] proportional by a second factor K to the voltage v 0 (t) of the grid, and

generator means capable to receive the output signal from the comparator means and a signal indicative of the phase of the grid for providing one or more signals for controlling the switching means.

25. A controller device according to claim 24 , wherein it is capable to perform a single switching cycle method comprising the following steps:

A. integrating, according to a time constant τ such that τ<T s , a voltage signal (V c −K g *v g ) equal to the difference between a control voltage V c and a voltage proportional by a first factor K g to the output voltage v g (t) of the source,

B. comparing a voltage drop [R s ·i o (t)], on a sensing resistor of resistance R s connected in series to the grid, with the sum of the result of the integration of step A with a voltage [K·v o (t)] proportional by a second factor K to the voltage v 0 (t) of the grid, and

C. generating one or more signals for controlling the switching means on the basis of the result of the comparison of step B,

the control voltage V c and the first factor K g being such as to fulfil the following first constraint:

V

c

≥

K

g

⁢

V

g

+

(

2

⁢

⁢

V

o

,

max

-

V

g

)

⁢

R

s

⁢

τ

2

⁢

⁢

L

,

where L is the output inductance seen by the inverter device, wherein the voltage signal integrated in step A is always positive, the input voltage of the switching means (M 1 -M 4 ) is higher than the output voltage thereof, and

K

⁡

(

1

-

P

o

⁡

(

S

)

α

·

P

g

,

MPP

⁡

(

S

max

)

)

·

(

1

-

γ

)

≤

V

m

V

g

⁢

❘

min

⁢

≤

V

m

V

g

⁢

❘

max

⁢

⁢

V

m

V

g

⁢

❘

min

⁢

≤

V

m

V

g

⁢

❘

max

⁢

≤

K

⁡

(

1

-

P

o

⁡

(

S

)

α

·

P

g

,

MPP

⁡

(

S

max

)

)

·

(

1

+

γ

)

where:

v

m

=

(

V

c

-

K

g

·

v

g

τ

)

·

T

s

P o (S) is the device output average power for a set S of operation conditions,

P g,MPP (S max ) is the maximum power deliverable by the source,

α is a first coefficient of overload, with α≧1, and

γ is a second coefficient, with γ<1.