Successive approximation register analog to digital converter (ADC) and method of adjusting delay thereof
A successive approximation register analog-to-digital converter includes: a digital-to-analog converter that generates an analog voltage based on a digital code; a comparator that receives the analog voltage; a control circuit that generates a digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on a comparison result of the comparator; a delay circuit that resets the comparator based on a signal transition generated by delaying the comparison result; and an adjustment circuit that counts a value indicating a number of the signal transition being generated during a cycle of the external clock signal and adjusts a delay of the delay circuit according to a counted value.
1. A successive approximation register analog-to-digital converter, comprising:
a digital-to-analog converter that generates an analog voltage based on a digital code;
a comparator that receives the analog voltage;
a control circuit that generates a digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on a comparison result of the comparator;
a delay circuit that resets the comparator based on a signal transition generated by delaying the comparison result; and
an adjustment circuit that counts a value indicating a number of the signal transition being generated during a cycle of the external clock signal and adjusts a delay of the delay circuit according to a counted value.
2. The successive approximation register analog-to-digital converter according to claim 1 , wherein the adjustment circuit includes:
a counter that counts the value; and
a determination circuit that determines whether the counted value is substantially equal to a predetermined value,
wherein the adjustment circuit adjusts the delay of the delay circuit according to a determination result of the determination circuit.
3. The successive approximation register analog-to-digital converter according to claim 1 , wherein the control circuit successively changes the digital code in synchronization with the signal transition.
4. The successive approximation register analog-to-digital converter according to claim 1 , further comprising:
a gate circuit that receives the comparison result, outputs a first signal according to an assert of the comparison result and outputs a second signal according to a negate of the comparison result,
wherein an output of the gate circuit is input to the delay circuit.
5. The successive approximation register analog-to-digital converter according to claim 1 , wherein the delay circuit includes:
a plurality of serially coupled delay elements; and
a selection circuit that selects at least one of the plurality of serially coupled delay elements according to an output of the adjustment circuit.
6. The successive approximation register analog-to-digital converter according to claim 1 , wherein the delay circuit includes:
one or more delay elements; and
another adjustment circuit that adjusts a drive current of the one or more delay element according to an output of the adjustment circuit.
7. The successive approximation register analog-to-digital converter according to claim 1 , wherein the digital-to-analog converter includes a capacitive digital-to-analog converter.
8. The successive approximation register analog-to-digital converter according to claim 1 , wherein the adjustment circuit increases the delay of the delay circuit when the count value is larger than a predetermined value, and decreases the delay of the delay circuit when the count value is smaller than the predetermined value.
9. A method of adjusting a delay in a successive approximation register analog-to-digital converter comprising:
generating analog voltages based on a digital code;
comparing the analog voltages to each other using a comparator to output a comparison result;
generating a digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the comparison result;
generating a signal transition by delaying the comparison result for a certain amount;
resetting the comparator by the signal transition;
counting a value indicating a number of the signal transition being generated during a cycle of the external clock signal; and
adjusting the amount according to the count value of the signal transition.
10. The method according to claim 9 , further comprising:
increasing the amount when the count value is larger than a predetermined value; and
decreasing the amount when the count value is smaller than the predetermined value.
11. The method according to claim 9 , wherein:
the digital code is successively changed in synchronization with the signal transition.