Dense array of field emitters using vertical ballasting structures
A field emitter array structure is provided. The field emitter array structure includes a plurality of vertical un-gated transistor structures formed on a semiconductor substrate. The semiconductor substrate includes a plurality of vertical pillar structures to define said un-gated transistor structures. A plurality of emitter structures are formed on said vertical un-gated transistor structures. Each of said emitter structures is positioned in a ballasting fashion on one of said vertical un-gated transistor structures so as to allow said vertical ungated transistor structure to effectively provide high dynamic resistance with large saturation currents.
1. A field emitter structure comprising:
a vertical un-gated transistor structure formed on a conducting substrate, said conducting substrate comprising a vertical pillar structure to define said vertical un-gated transistor structure, wherein said conducting substrate is etched to fill a gap between said vertical pillar structure with a plurality of dielectric layers;
an emitter structure formed on said vertical un-gated transistor structure, said emitter structure is positioned in a ballasting fashion on said vertical un-gated transistor structure so as to allow said vertical un-gated transistor to provide high dynamic resistance with large saturation currents.
2. A field emitter array structure comprising:
a plurality of vertical un-gated transistor structures formed on a conducting substrate, said conducting substrate comprising a plurality of vertical pillar structures to define said vertical un-gated transistor structures, wherein said conducting substrate is etched to fill a gap between said vertical pillar structure with a plurality of dielectric layers;
a plurality of emitter structures formed on the said vertical un-gated transistor structures, each of said emitter structures is positioned in a ballasting fashion on one of said vertical un-gated transistor structures so as to allow said vertical un-gated field effect transistor structures to provide high dynamic resistance with large saturation currents.
3. The field emitter array structure of claim 2 further comprising a plurality of gate structures associated with each of said emitter structures.
4. The field emitter array structure of claim 2 , wherein said emitter structures comprise of carbon or Si nanotubes or Si.
5. The field emitter array structure of claim 2 , wherein each of said vertical un-gated transistor structures are separated by a filled oxide trench.
6. The field emitter array structure of claim 2 , wherein said conducting substrate comprises a n-type silicon substrate.
7. The field emitter array structure of claim 2 , wherein said vertical un-gated transistor structures behave similarly to a current limiter.
8. The field emitter array structure of claim 2 further comprising an anode structure coupled to said field emitter array structure.
9. The field emitter array structure of claim 2 , said vertical pillar structures comprise Si.
10. The field emitter array structure of claim 2 , wherein said vertical un-gated transistor structures comprise vertical un-gated FET structures.
11. The field emitter array structure of claim 2 , wherein said vertical un-gated FET structures behave similarly to current sources.
12. A method of forming a field emitter array structure comprising:
forming a plurality of vertical un-gated transistor structures on a conducting substrate, said conducting substrate comprising a plurality of vertical pillar structures to define said vertical un-gated transistor structures, wherein said conducting substrate is etched to fill a gap between said vertical pillar structure with a plurality of dielectric layers; and
forming a plurality of emitter structures on said vertical un-gated transistor structures, each of said emitter structures is positioned in a ballasting fashion on one of said vertical un-gated transistor structures so as to allow said vertical un-gated transistor structure to provide high dynamic resistance with large saturation currents.
13. The method of claim 12 further comprising a plurality of gate structures associated with each of said emitter structures.
14. The method of claim 12 , wherein said emitter structures comprise of carbon or Si nanotubes or Si.
15. The method of claim 12 , wherein each of said vertical un-gated transistor structures are separated by an oxide filled trench.
16. The method of claim 12 , wherein said conducting substrate comprises a n-type silicon substrate.
17. The method of claim 12 , wherein said vertical un-gated transistor structures behave similarly to a current limiter.
18. The method of claim 12 further comprising an anode structure coupled to said field emitter array structure.
19. The method of claim 12 , said vertical pillar structures comprise Si.
20. The method of claim 12 , wherein said vertical un-gated transistor structures comprise vertical un-gated FET structures.
21. The method of claim 12 , wherein said vertical un-gated FET structures behave similarly to current sources.