IP Library › Granted Patent US 8,202,799
Granted Patent B2
US 8,202,799 · App. 12/833,595 · Granted Jun 19, 2012

Methods of manufacturing metal-silicide features

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,202,799
App. No.
12/833,595
Granted
Jun 19, 2012
Kind
B2
Abstract

A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.

Claims (29)

1. A method comprising:

forming a dielectric layer over a substrate having a plurality of openings therein; and

depositing a plurality of metal-silicide layers, each of the metal-silicide layers substantially conforming to one of the plurality of openings, wherein the depositing the plurality of metal-silicide layers includes performing a co-sputtering deposition process, wherein depositing the metal-silicide layers includes varying a concentration of a metal constituent relative to a concentration of a silicide constituent by varying biases of a metal target and a silicon-containing target, such that the metal-silicide layers exhibit varying electrical characteristics.

2. The method of claim 1 wherein the co-sputtering deposition process employs the metal target and the silicon-containing target.

3. The method of claim 1 wherein the varying the concentration of the metal constituent relative to the concentration of the silicide constituent, such that the metal-silicide layers exhibit varying electrical characteristics includes varying the concentrations of the metal and silicide constituents to achieve metal-silicide layers that exhibit varying work functions.

4. The method of claim 1 wherein the forming the dielectric layer over the substrate having a plurality of openings therein includes:

forming a plurality of dummy features over the substrate;

depositing the dielectric layer over the substrate, such that the dielectric layer surrounds the dummy features; and

removing the dummy features, such that the plurality of openings are formed in the dielectric layer.

5. A method comprising:

forming a dielectric layer substantially surrounding a dummy feature located over a substrate;

removing the dummy feature to form an opening in the dielectric layer; and

depositing a metal-silicide layer substantially conforming to the opening, wherein the depositing the metal-silicide layer includes depositing the metal-silicide layer by a co-sputtering deposition process that varies a concentration gradient between a metal constituent and a silicide constituent by varying biases of the metal constituent and the silicide constituent such that a greater concentration of the silicon constituent forms adjacent a bottom of the opening relative to the metal constituent.

6. The method of claim 5 , wherein depositing the metal-silicide layer substantially conforming to the opening includes the metal-silicide layer completely filling the opening.

7. The method of claim 5 , wherein depositing the metal-silicide layer substantially conforming to the opening includes the metal-silicide layer having a substantially u-shaped profile within the opening.

8. The method of claim 7 , wherein the metal-silicide layer having the substantially u-shaped profile defines a recess within the opening, the method further comprising:

forming a conductive material in the recess.

9. A method comprising:

forming a dielectric layer having an opening therein over a substrate; and

forming a metal-silicide layer substantially conforming to the opening, wherein forming the metal-silicide layer is performed by a co-sputtering deposition process, wherein forming the metal-silicide layer includes varying biases of a metal target and a silicon-containing target to achieve a concentration gradient between a metal constituent and a silicide constituent, such that a greater concentration of one of the metal and silicide constituent forms near a bottom of the opening and a greater concentration of the other of the metal and silicide constituent forms distal from the bottom of the opening.

10. The method of claim 9 , wherein the co-sputtering deposition process employs the metal target and the silicon-containing target.

11. The method of claim 9 , wherein a greater concentration of the silicide constituent forms adjacent the bottom of the opening relative to the metal constituent.

12. The method of claim 9 , wherein a greater concentration of the metal constituent forms adjacent the bottom of the opening relative to the silicide constituent.

13. The method of claim 9 , wherein forming the dielectric layer includes forming the dielectric layer substantially surrounding a dummy feature located over the substrate and removing the dummy feature to form the opening in the dielectric layer.

14. The method of claim 9 , furthering comprising depositing a gate dielectric within the opening.

15. The method of claim 9 , furthering comprising annealing the metal-silicide layer.

16. The method of claim 9 , wherein the metal target is selected from the group consisting of cobalt, nickel, tungsten, bismuth, titanium, tantalum, aluminum, gold, silver, and combinations thereof.

17. The method of claim 9 ,wherein forming the metal-silicide layer substantially conforming to the opening includes the metal-silicide layer completely filling the opening.

18. The method of claim 9 , wherein forming the metal-silicide layer substantially conforming to the opening includes the metal-silicide layer having a substantially u-shaped profile within the opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2014
From: LIN, CHEN-TUNG; CHANG, CHIH-WEI; WU, CHII-WEI; WANG, MEI-YUN; CHUANG, CHIANG-MING; SHUE, SHAU-LIN
To: TAIWAN SEMICONDCUTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 033576/0836 →
Continuity (3)
Division 11838376 · Aug 14, 2007
Division 10872343 · Jun 18, 2004
Related Publication 20100273324A1 · Oct 28, 2010