Methods of manufacturing memory devices

1. A method of manufacturing a memory device, the method comprising:

providing a substrate;

forming a number of memory sectors on the substrate, each of the memory sectors coupled to an adjacent one via a first diffused region in the substrate and coupled to another adjacent one via at least one second diffused region in the substrate;

forming a first dielectric layer on the memory sectors;

forming a first conductive structure through the first dielectric layer to the first diffused region, and forming at least one second conductive structure through the first dielectric layer to the at least one second diffused region;

forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure;

etching back the first conductive structure;

removing the patterned first mask layer;

forming a second dielectric layer on the first dielectric layer and the at least one second conductive structure; and

leveling the second dielectric layer, wherein leveling the second dielectric layer exposes the at least one second conductive structure, further comprising:

forming a conductive layer on the leveled second dielectric layer and the at least one second conductive structure;

forming a patterned second mask layer on the conductive layer, the patterned second mask layer masking portions of the conductive layer over the at least one second conductive structure; and

removing the exposed portions of the conductive layer, resulting in a patterned conductive layer.

2. The method of claim 1 , wherein each of the at least one second conductive structure has a shape tapered toward one of the at least one second diffused region, and the patterned conductive layer includes conductive lines each having a shape tapered from one of the at least one second conductive structure.

3. The method of claim 1 , wherein each of the memory sectors includes a first select gate, a second select gate and a number of NAND strings between the first select gate and the second select gate.

4. A method of manufacturing a memory device, the method comprising:

providing a substrate;

forming a number of memory sectors on the substrate, each of the memory sectors coupled to an adjacent one via a first diffused region in the substrate and coupled to another adjacent one via at least one second diffused region in the substrate;

forming a first dielectric layer on the memory sectors;

forming a first conductive structure through the first dielectric layer to the first diffused region, and forming at least one second conductive structure through the first dielectric layer to the at least one second diffused region;

forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure;

etching back the first conductive structure;

removing the patterned first mask layer;

forming a second dielectric layer on the first dielectric layer and the at least one second conductive structure; and

leveling the second dielectric layer, wherein leveling the second dielectric layer leaves the at least one second conductive structure unexposed, further comprising:

forming a patterned second mask layer on the leveled second dielectric layer, the patterned second mask layer exposing portions of the leveled second dielectric layer over the at least one second conductive structure; and

removing the exposed portions of the leveled second dielectric layer, resulting in a patterned second dielectric layer;

removing the patterned second mask layer; and

forming a conductive layer on the patterned second dielectric layer.

5. The method of claim 4 , wherein each of the at least one second conductive structure has a shape tapered toward one of the at least one second diffused region, and the conductive layer includes conductive lines each having a shape tapered toward one of the at least one second conductive structure.

6. A method of manufacturing a memory device, the method comprising:

providing a substrate;

forming a number of memory sectors on the substrate, each of the memory sectors coupled to an adjacent one via a first diffused region in the substrate and coupled to another adjacent one via at least one second diffused region in the substrate;

forming a first dielectric layer on the memory sectors;

forming a first opening through the first dielectric layer, exposing the first diffused region, and at least one second opening through the first dielectric layer, exposing the at least one second diffused region;

forming a first conductive layer on the first dielectric layer, the first conductive layer filling the first opening, resulting in a first conductive structure, and filling the at least one second opening, resulting in at least one second conductive structure;

forming a patterned first mask layer on the first conductive layer, the patterned first mask layer exposing a portion of the first conductive layer over the first conductive structure;

etching back the exposed portion of the first conductive layer;

etching off the first conductive layer on the first dielectric layer so that the first conductive structure is etched back;

removing the patterned first mask layer;

forming a second dielectric layer on the first dielectric layer and the at least one second conductive structure; and

leveling the second dielectric layer, wherein leveling the second dielectric layer exposes the at least one second conductive structure, further comprising:

forming a second conductive layer on the leveled second dielectric layer and the at least one second conductive structure;

forming a patterned second mask layer on the second conductive layer, the patterned second mask layer masking portions of the second conductive layer over the at least one second conductive structure; and

removing the exposed portions of the second conductive layer, resulting in a patterned second conductive layer.

7. The method of claim 6 , wherein the patterned first mask layer is removed during etching back the exposed portion of the first conductive layer.

8. The method of claim 6 , wherein each of the at least one second conductive structure has a shape tapered toward one of the at least one second diffused region, and the patterned second conductive layer includes conductive lines each having a shape tapered from one of the at least one second conductive structure.

9. A method of manufacturing a memory device, the method comprising:

providing a substrate;

forming a number of memory sectors on the substrate, each of the memory sectors coupled to an adjacent one via a first diffused region in the substrate and coupled to another adjacent one via at least one second diffused region in the substrate;

forming a first dielectric layer on the memory sectors;

forming a first opening through the first dielectric layer, exposing the first diffused region, and at least one second opening through the first dielectric layer, exposing the at least one second diffused region;

forming a first conductive layer on the first dielectric layer, the first conductive layer filling the first opening, resulting in a first conductive structure, and filling the at least one second opening, resulting in at least one second conductive structure;

forming a patterned first mask layer on the first conductive layer, the patterned first mask layer exposing a portion of the first conductive layer over the first conductive structure;

etching back the exposed portion of the first conductive layer;

etching off the first conductive layer on the first dielectric layer so that the first conductive structure is etched back;

removing the patterned first mask layer;

forming a second dielectric layer on the first dielectric layer and the at least one second conductive structure; and

leveling the second dielectric layer, wherein leveling the second dielectric layer leaves the at least one second conductive structure unexposed, further comprising:

forming a patterned second mask layer on the leveled second dielectric layer, the patterned second mask layer exposing portions of the leveled second dielectric layer over the at least one second conductive structure; and

removing the exposed portions of the leveled second dielectric layer, resulting in a patterned second dielectric layer;

removing the patterned second mask layer; and

forming a second conductive layer on the patterned second dielectric layer.

10. The method of claim 9 , wherein each of the at least one second conductive structure has a shape tapered toward one of the at least one second diffused region, and the second conductive layer includes conductive lines each having a shape tapered toward one of the at least one second conductive structure.

11. A method of manufacturing a memory device, the method comprising:

providing a substrate;

forming a number of memory sectors on the substrate, each of the memory sectors coupled to an adjacent one via a first diffused region in the substrate and coupled to another adjacent one via at least one second diffused region in the substrate;

forming a first dielectric layer on the memory sectors;

forming a first opening through the first dielectric layer, exposing the first diffused region, and at least one second opening through the first dielectric layer, exposing the at least one second diffused region;

forming a first conductive layer on the first dielectric layer, the first conductive layer filling the first opening, resulting in a first conductive structure, and filling the at least one second opening, resulting in at least one second conductive structure;

forming a patterned first mask layer on the first conductive layer, the patterned first mask layer exposing a portion of the first conductive layer over the first conductive structure;

etching back the first conductive structure through the exposed portion of the first conductive layer, using the patterned first mask layer as a mask;

removing the patterned first mask layer;

forming a second dielectric layer on the first dielectric layer and the at least one second conductive structure; and

leveling the second dielectric layer, wherein leveling the second dielectric layer exposes the at least one second conductive structure, further comprising:

forming a second conductive layer on the leveled second dielectric layer and the at least one second conductive structure;

forming a patterned second mask layer on the second conductive layer, the patterned second mask layer masking portions of the second conductive layer over the at least one second conductive structure; and

removing the exposed portions of the second conductive layer, resulting in a patterned second conductive layer.

12. The method of claim 11 , wherein each of the at least one second conductive structure has a shape tapered toward one of the at least one second diffused region, and the patterned second conductive layer includes conductive lines each having a shape tapered from one of the at least one second conductive structure.

13. A method of manufacturing a memory device, the method comprising:

providing a substrate;

forming a number of memory sectors on the substrate, each of the memory sectors coupled to an adjacent one via a first diffused region in the substrate and coupled to another adjacent one via at least one second diffused region in the substrate;

forming a first dielectric layer on the memory sectors;

forming a first opening through the first dielectric layer, exposing the first diffused region, and at least one second opening through the first dielectric layer, exposing the at least one second diffused region;

forming a first conductive layer on the first dielectric layer, the first conductive layer filling the first opening, resulting in a first conductive structure, and filling the at least one second opening, resulting in at least one second conductive structure;

forming a patterned first mask layer on the first conductive layer, the patterned first mask layer exposing a portion of the first conductive layer over the first conductive structure;

etching back the first conductive structure through the exposed portion of the first conductive layer, using the patterned first mask layer as a mask;

removing the patterned first mask layer;

forming a second dielectric layer on the first dielectric layer and the at least one second conductive structure; and

leveling the second dielectric layer, wherein leveling the second dielectric layer leaves the at least one second conductive structure unexposed, further comprising:

forming a patterned second mask layer on the leveled second dielectric layer, the patterned second mask layer exposing portions of the leveled second dielectric layer over the at least one second conductive structure; and

removing the exposed portions of the leveled second dielectric layer, resulting in a patterned second dielectric layer;

removing the patterned second mask layer; and

forming a second conductive layer on the patterned second dielectric layer.

14. The method of claim 13 , wherein each of the at least one second conductive structure has a shape tapered toward one of the at least one second diffused region, and the second conductive layer includes conductive lines each having a shape tapered toward one of the at least one second conductive structure.