Power semiconductor device
A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer.
1. A power semiconductor device comprising:
a first semiconductor layer of a first or second conductivity type;
a second semiconductor layer of the first conductivity type formed on the first semiconductor layer;
a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer;
at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer;
at least one insulator buried in the at least one trench;
a first main electrode electrically connected to the first semiconductor layer; and
a second main electrode electrically connected to the third semiconductor layer;
wherein the at least one trench is formed so as to have a vortex shape when viewed from above the second semiconductor layer.
2. The device according to claim 1 , wherein a width of the at least one trench is equal to or larger than one tenth of a depth of the at least one trench.
3. The device according to claim 1 , wherein a relation d >t/(n+1) is satisfied where d is a depth of the at least one trench, t is a thickness of the second semiconductor layer, and n is a number of pieces of sections of the at least one trench which exist on one side of the third semiconductor layer on an arbitrary cross section crossing the third semiconductor layer.
4. The device according to claim 1 , further comprising:
a floating electrode formed in the at least one trench and having side surfaces and a bottom surface covered by the at least one insulator.
5. The device according to claim 1 , further comprising:
a gate electrode formed on the second and third semiconductor layers via a gate insulator.
6. The device according to claim 1 , further comprising:
a plurality of fourth semiconductor layers of the second conductivity type selectively formed on the surface of the second semiconductor layer in a region sandwiched between parts of the at least one trench.
7. The device according to claim 6 , wherein the fourth semiconductor layers are formed only inside the region sandwiched between the parts of the at least one trench.
8. The device according to claim 6 , wherein the fourth semiconductor layers are formed inside and outside the region sandwiched between the parts of the at least one trench.
9. The device according to claim 6 , further comprising:
a plurality of field plate electrodes formed on the fourth semiconductor layers and electrically connected to the fourth semiconductor layers.
10. The device according to claim 6 , wherein a surface of the region sandwiched between the parts of the at least one trench includes areas where the second semiconductor layer is exposed and areas where the fourth semiconductor layers are exposed, alternately along the at least one trench.
11. The device according to claim 10 , wherein a distance between the fourth semiconductor layers adjacent along the at least one trench is shorter than a length of each of the fourth semiconductor layers along the at least one trench.
12. The device according to claim 10 , wherein the region sandwiched between the parts of the at least one trench includes at least ten of the fourth semiconductor layers, while the at least one trench makes one trip around the third semiconductor layer.
13. The device according to claim 10 , wherein the fourth semiconductor layers are arranged so as to be opposed to different fourth semiconductor layers via the at least one trench.
14. The device according to claim 1 , further comprising:
a fifth semiconductor layer of the second conductivity type formed on sidewalls of the at least one trench and to be depleted by applying a predetermined voltage.
15. The device according to claim 14 , wherein the fifth semiconductor layer is formed only on the sidewalls of the at least one trench.
16. The device according to claim 14 , wherein the fifth semiconductor layer is formed on the sidewalls and a bottom part of the at least one trench.