Layout methods of integrated circuits having unit MOS devices
View Patent ↗A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
1. A semiconductor structure comprising:
an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns, wherein each of the unit MOS devices comprises:
an active region laid out in a row direction, wherein unit MOS devices in each row of the array have substantially identical dimensions; and
a gate electrode laid out in a column direction;
a first unit MOS device in the array;
a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types;
a third unit MOS device and a fourth unit MOS device in a same column of the array and next to each other;
a first contact electrically connecting sources of the third and the fourth unit MOS devices;
a second contact electrically connecting drains of the third and the fourth unit MOS devices, wherein gates of the third and the fourth unit MOS devices are electrically connected; and
insulating regions isolating the active region of each of the unit MOS devices in the array from active regions of remaining ones of the MOS devices in the array, wherein substantially no active regions of neighboring unit MOS devices are physically interconnected as an integrated active region.
2. The semiconductor structure of claim 1 , wherein all unit MOS devices in the array are identical to each other in dimensions.
3. The semiconductor structure of claim 1 , wherein the array comprises a first sub region and a second sub region, and wherein unit MOS devices in the first sub region have different dimensions than unit MOS devices in the second sub region.
4. The semiconductor structure of claim 1 , wherein the array comprises a first sub region and a second sub region having different numbers of unit MOS devices.
5. The semiconductor structure of claim 1 , wherein all active regions of the unit MOS devices are substantially rectangular.
6. The semiconductor structure of claim 1 , wherein the array further comprises a fifth unit MOS device in the same column and next to the fourth unit MOS device, and wherein the semiconductor structure further comprises:
a third contact electrically connecting sources of the fourth and the fifth unit MOS devices; and
a fourth contact electrically connecting drains of the fourth and the fifth unit MOS devices, wherein gates of the third, the fourth and the fifth unit MOS devices are electrically connected.
7. The semiconductor structure of claim 1 further comprising an additional array identical to the array, wherein contacts and contact pickups in the additional array are substantially different from contacts and contact pickups in the array, and wherein the array and the additional array form different integrated circuits.
8. The semiconductor structure of claim 1 , wherein the unit MOS devices are planar MOS devices.
9. The semiconductor structure of claim 1 , wherein the unit MOS devices are Fin field-effect transistors.
10. The semiconductor structure of claim 1 , wherein the array is not a memory array.
11. A semiconductor structure comprising:
an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns, wherein each of the unit MOS devices comprises:
an active region laid out in a row direction; and
a gate electrode laid out in a column direction;
a first unit MOS device in the array;
a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types;
a third unit MOS device and a fourth unit MOS device in a same column of the array and next to each other;
a first contact electrically connecting sources of the third and the fourth unit MOS devices; and
a second contact electrically connecting drains of the third and the fourth unit MOS devices, wherein gates of the third and the fourth unit MOS devices are electrically connected.
12. The semiconductor structure of claim 11 , wherein the unit MOS devices in the array are identical to each other in dimensions.
13. The semiconductor structure of claim 11 , wherein the array comprises a first sub region and a second sub region, and wherein unit MOS devices in the first sub region have different dimensions than unit MOS devices in the second sub region.
14. The semiconductor structure of claim 11 , wherein the active regions of the unit MOS devices in the array are isolated from each other by insulating regions, and wherein substantially no active region exists between the active regions of the unit MOS devices.
15. The semiconductor structure of claim 11 further comprising:
a fifth unit MOS device in the same column of the array as, and next to, the fourth unit MOS device;
a third contact electrically connecting sources of the fourth and the fifth unit MOS devices; and
a fourth contact electrically connecting drains of the fourth and the fifth unit MOS devices, wherein gates of the third, the fourth and the fifth unit MOS devices are electrically connected.
16. The semiconductor structure of claim 11 further comprising an additional array identical to the array, wherein contacts and contact pickups in the additional array are substantially different from contacts and contact pickups in the array, and wherein the array and the additional array form different integrated circuits.