Flip chip package having enhanced thermal and mechanical performance
View Patent ↗A flip chip semiconductor package is provided. In one embodiment, the flip chip semiconductor package comprises a first substrate having a first surface and a second surface opposite the first surface, a semiconductor chip mounted on the first surface of the first substrate by solder bumps, a thermally-conductive stiffener mounted above the first surface of the first substrate and around the chip to define a cavity region therebetween, one or more molding compound material disposed in the cavity region, and a second substrate mounted to the second surface of the first substrate by solder balls.
1. A semiconductor package structure, comprising:
a first substrate having a first surface and a second surface opposite the first surface;
a semiconductor chip mounted on the first surface of the first substrate by solder bumps;
a thermally-conductive stiffener mounted above the first surface of the first substrate and around the chip to define a cavity region therebetween;
one or more molding compound material disposed in the cavity region;
an underfill layer in a gap between the semiconductor chip and the first substrate, wherein the one or more molding compound material is disposed between the underfill layer and the thermally-conductive stiffener; and
a second substrate mounted to the second surface of the first substrate by solder balls.
2. The semiconductor package structure of claim 1 , further comprising a heat spreader mounted over the stiffener for sealing the semiconductor chip therein.
3. The semiconductor package structure of claim 2 , further comprising a thermal interface material disposed between the semiconductor chip and the heat spreader.
4. The semiconductor package of claim 1 , wherein the molding compound material comprises an epoxy resin material, polyester material, thermoplastic material, a dielectric material, metal, ceramic, or silicon-containing material.
5. The semiconductor package of claim 1 , wherein the molding compound has a thickness in the range of from about 0.5 mm to about 5 mm.
6. The semiconductor package of claim 1 , wherein the molding compound material has a coefficient of thermal expansion (CTE) substantially equal to the CTE of the first substrate.
7. The semiconductor package of claim 1 , wherein the molding compound material has a CTE substantially equal to the coefficients of thermal expansion of the semiconductor chip and the first substrate.
8. A flip chip package, comprising:
a first substrate having a first surface and a second surface opposite the first surface;
a semiconductor chip mounted on the first surface of the first substrate by solder bumps;
a thermally-conductive stiffener mounted above the first surface of the first substrate and around the chip to define a cavity region therebetween;
one or more molding compound material disposed in the cavity region directly on the first surface;
an underfill layer in a gap between the semiconductor chip and the first substrate, wherein the one or more molding compound material is disposed between the underfill layer and the thermally-conductive stiffener; and
a second substrate mounted to the second surface of the first substrate by solder balls.
9. The flip chip package of claim 8 , further comprising a heat spreader mounted over the stiffener for sealing the semiconductor chip therein.
10. The flip chip package of claim 9 , further comprising a thermal interface material disposed between the semiconductor chip and the heat spreader.
11. The flip chip package of claim 8 , wherein the molding compound material comprises an epoxy resin material, polyester material, thermoplastic material, a dielectric material, metal, ceramic, or silicon-containing material.
12. The flip chip package of claim 8 , wherein the molding compound has a thickness in the range of from about 0.5 mm to about 5 mm.
13. The flip chip package of claim 8 , wherein the molding compound material has a coefficient of thermal expansion (CTE) substantially equal to the CTE of the first substrate.
14. The flip chip package of claim 8 , wherein the molding compound material has a CTE substantially equal to the coefficients of thermal expansion of the semiconductor chip and the first substrate.
15. A method of forming a semiconductor flip chip package, comprising:
mounting a semiconductor chip on a first surface of a first substrate by solder bumps;
mounting a thermally-conductive stiffener above the first surface of the first substrate and around the chip to define a cavity region therebetween;
injecting a molding compound material having a low viscous state into the cavity region;
curing the molding compound material to harden the molding compound material;
filling a gap between the semiconductor chip and the first substrate with an underfill layer, wherein the one or more molding compound material is disposed between the underfill layer and the thermally-conductive stiffener; and
mounting a second substrate to a second surface, opposite the first surface, of the first substrate by solder balls.
16. The method of claim 15 , further comprising mounting a heat spreader over the stiffener for sealing the semiconductor chip therein.
17. The method of claim 15 , wherein filling the gap between the semiconductor chip and the first substrate with the underfill layer further comprises curing the underfill layer.
18. The semiconductor package of claim 2 , wherein the heat spreader and the thermally-conductive stiffener comprise a same material.
19. The semiconductor package of claim 3 , wherein the thermal interface material comprises a thermal grease type material.
20. The flip chip package of claim 10 , wherein the thermal interface material comprises a thermal grease type material.