Flash memory device and manufacturing method of the same
A flash memory device and a method for manufacturing the same are provided. The flash memory device can include first and second memory gates on a substrate, an oxide layer on sides of and on the substrate outside of the first and second memory gates, a source poly contact between the first and second memory gates, first and second select gates outside the first and second memory gates, a drain region outside the first and second select gates, and a metal contact on the drain region and the source poly contact.
1. A flash memory device comprising:
a first memory gate and a second memory gate on a substrate;
an oxide layer along sides of the first memory gate, along sides of the second memory gate, on the substrate outside of the first memory gate, and on the substrate outside of the second memory gate;
a source region filled a with poly on the substrate between the first memory gate and the second memory gate;
a self-aligned source poly contact between the first memory gate and the second memory gate;
a first select gate outside of the first memory gate;
a second select gate outside of the second select gate;
drain regions outside the first select gate and the second select gate; and
metal contacts on the drain regions and on the source poly contact.
2. The flash memory device according to claim 1 , further comprising a source region under and in contact with the source poly contact; wherein the source poly contact serves as a source contact; and wherein, during operation of the flash memory device, bias is applied to the source poly contact so that the bias is transferred to the source region through the source poly contact.
3. The flash memory device according to claim 1 , further comprising a halo ion implantation region and an LDD ion implantation region on the substrate between the first memory gate and the second memory gate.
4. The flash memory device according to claim 1 , further comprising the oxide layer on the substrate under the first select gate and on the substrate under the second select gate.
5. The flash memory device according to claim 4 , wherein the oxide layer serves as a gate oxide layer for the first select gate and the second select gate.
6. The flash memory device according to claim 1 , further comprising a source region in the substrate between the first memory gate and the second memory gate.
7. The flash memory device according to claim 1 , wherein, during operation, the flash memory device performs a read operation in a direction reverse to a program direction.
8. The flash memory device according to claim 1 , wherein, during operation, the flash memory device controls programming current by using bias applied to the first select gate and the second select gate.
9. The flash memory device according to claim 1 , wherein, during operation, the flash memory device applies back bias to a source to control programming current.