Semiconductor memory device and test method therefor

1. A semiconductor memory device comprising:

a first SRAM cell and a second SRAM cell;

a first bit line pair provided with the first SRAM cell;

a second bit line pair provided with the second SRAM cell;

a sense amplifier provided between the first bit line pair and the second bit line pair;

a first switch circuit provided between the first bit line pair and the second bit line pair; and

a controller that controls the first switch circuit to render the first bit line pair and the second bit line pair conductive at a first timing, in a case of testing the first SRAM cell.

2. The semiconductor memory device according to claim 1 ,

wherein the first switch circuit comprises:

a first bit line selection circuit provided between the sense amplifier and the first bit line pair; and

a second bit line selection circuit provided between the sense amplifier and the second bit line pair.

3. The semiconductor memory device according to claim 1 , where the sense amplifier is connected in parallel with the first switch circuit.

4. The semiconductor memory device according to claim 2 , wherein the first bit line pair and the second bit line pair are opposed to each other through the sense amplifier.

5. The semiconductor memory device according to claim 3 , wherein the first bit line pair and the second bit line pair are opposed to each other through the sense amplifier.

6. The semiconductor, memory device according to claim 1 , further comprising:

a third SRAM cell;

a third bit line pair provided with the third SRAM cell; and

a second switch circuit provided between the second bit line pair and the third bit line pair.

7. The semiconductor memory device according to claim 1 , wherein the number of memory cells provided between the first bit line pair is in a range from 8 to 32.

8. The semiconductor memory device according to claim 1 , wherein the number of memory cells provided between the second bit line pair is in a range from 8 to 32.

9. A test method for a semiconductor memory device, the semiconductor memory device comprising:

a first bit line pair provided with a first SRAM cell; a second bit line pair provided with a second SRAM cell, and a sense amplifier provided between the first bit line pair and the second bit line pair, the test method comprising:

in a case of testing the first SRAM cell,

rendering the first bit line pair and the second bit line pair conductive at a first timing; and

performing a read operation for the first SRAM cell at a second timing subsequent to the first timing.

10. A test method for a semiconductor memory device, the semiconductor memory device comprising:

a first bit line pair provided with a first SRAM cell; and a second bit line pair provided with a second SRAM cell, the test method comprising:

in a case of testing the first SRAM cell,

rendering the first bit line pair and the second bit line pair conductive at a first timing; and

performing a read operation for the first SRAM cell at a second timing subsequent to the first timing,

wherein during a period when the first bit line pair and the second bit line pair are rendered conductive and during the read operation for the first SRAM cell, the first bit line pair is not precharged.

11. The test method for a semiconductor memory device according to claim 9 , wherein during a period between the first timing and the second timing, the first bit line pair is precharged.

12. The test method for a semiconductor memory device according to claim 9 , wherein, prior to the first timing, a write operation for the first SRAM cell and the read operation therefor are performed.

13. A test method for a semiconductor memory device, the semiconductor memory device comprising:

a first bit line pair provided with a first SRAM cell; and a second bit line pair provided with a second SRAM cell, the test method comprising:

in a ease of testing the first SRAM cell,

rendering the first bit line pair and the second bit line pair conductive at a first timing; and

performing a read operation for the first SRAM cell at a second timing subsequent to the first timing,

wherein, prior to the first timing, a write operation for the first SRAM cell and the read operation therefor are performed,

wherein during the write operation and the read operation prior to the first timing, the first bit line pair is not precharged.