IP Library › Granted Patent US 8,286,062
Granted Patent B2
US 8,286,062 · App. 13/433,226 · Granted Oct 9, 2012

Method and apparatus of encoding and decoding data using low density parity check code in a wireless communication system

Assignee: LG Electronics Inc.
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Quick Facts
Patent No.
US 8,286,062
App. No.
13/433,226
Granted
Oct 9, 2012
Kind
B2
Abstract

A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’.

Claims (661)

1. An apparatus for encoding input data using low density parity check (LDPC) code, the apparatus comprising:

a parity check matrix generation module for generating a parity check matrix by replacing each integer value of a first base matrix with a corresponding matrix, wherein the first base matrix is as follows when the code rate is 2/3:

2

-

1

19

-

1

47

-

1

48

-

1

36

-

1

82

-

1

47

-

1

69

-

1

88

-

1

33

-

1

3

-

1

16

-

1

37

-

1

10

-

1

86

-

1

62

-

1

28

-

1

85

-

1

16

-

1

34

-

1

28

-

1

32

-

1

81

-

1

27

-

1

88

-

1

5

-

1

23

-

1

29

-

1

15

-

1

30

-

1

66

-

1

24

-

1

50

-

1

30

-

1

65

-

1

54

-

1

14

-

1

0

-

1

30

-

1

32

-

1

0

-

1

15

-

1

56

-

1

85

-

1

5

-

1

6

-

1

0

-

1

47

-

1

13

-

1

61

-

1

84

-

1

55

-

1

⁢

-

1

15

-

1

X

0

-

1

-

1

-

1

-

1

-

1

-

1

40

-

1

48

-

1

0

0

-

1

-

1

-

1

-

1

-

1

-

1

73

-

1

-

1

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1

0

0

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1

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1

-

1

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1

56

-

1

37

-

1

-

1

-

1

0

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-

1

-

1

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1

-

1

62

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1

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1

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1

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1

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1

0

0

-

1

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1

74

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1

0

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1

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1

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1

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1

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1

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52

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1

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1

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1

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1

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0

78

-

1

41

X

-

1

-

1

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1

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1

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1

-

1

0

,

wherein “−1” indicates a zero matrix having a z max ×z max size,

wherein “0” indicates an identity matrix having the z max ×z max size,

wherein a positive integer indicates a first permutation matrix having the z max ×z max size that is generated by circular shifting the identity matrix by the positive integer, and

wherein “X” denotes an integer from 0 to 95; and

an encoder for encoding the input data using the parity check matrix.

2. The apparatus of claim 1 , wherein the encoder comprises:

a memory module for storing the first base matrix;

a base matrix generation module for generating a second base matrix by replacing each first value corresponding to each element of the first base matrix with a second value corresponding to each element of the second base matrix, the second value an integer that indicates either a zero matrix or a second permutation matrix having a z×z size, wherein z is smaller than z max ;

a parity check matrix generation module for generating the parity check matrix by replacing each second value of the second base matrix with a corresponding second permutation matrix or the zero matrix having the z×z size; and

an encoding module for encoding the input data using the parity check matrix.

3. The apparatus of claim 2 , wherein:

the second value is either a non-negative integer or “−1;” and

the parity check matrix generation module comprises:

means for replacing each second value of “−1” with the zero matrix having the z×z size;

means for replacing each second value of a positive integer with a second permutation matrix having the z×z size, the second permutation matrix altered from an identity matrix having the z×z size according to the positive integer; and

means for replacing each second value of a zero with a second permutation matrix that is the identity matrix having the z×z size.

4. The apparatus of claim 3 , wherein the second permutation matrix is altered by circular shifting either each entire row or each entire column of the identity matrix a number of intervals equal to the positive integer.

5. The apparatus of claim 2 , wherein each of the first and second permutation matrixes is defined as having a row weight and column weight of “1.”

6. The apparatus of claim 2 , wherein each second value is determined based on the following equation:

shift( z )=floor(shift( z max ) z/z max ),

wherein “shift (z max )” is the first value,

wherein “shift(z)” is the second value, and

wherein “floor (x)” indicates a nearest integer from x toward negative infinity.

7. The apparatus of claim 1 , wherein “X” is 95.

8. An apparatus for decoding encoded data using low density parity check (LDPC) code, the method comprising:

a parity check matrix generation module for generating a parity check matrix by replacing each integer value of a first base matrix with a corresponding matrix, wherein the first base matrix is as follows when the code rate is 2/3:

2

-

1

19

-

1

47

-

1

48

-

1

36

-

1

82

-

1

47

-

1

15

-

1

X

0

-

1

-

1

-

1

-

1

-

1

-

1

-

1

69

-

1

88

-

1

33

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1

3

-

1

16

-

1

37

-

1

40

-

1

48

-

1

0

0

-

1

-

1

-

1

-

1

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1

10

-

1

86

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1

62

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1

28

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1

85

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1

16

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1

34

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1

73

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1

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1

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32

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32

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15

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56

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1

85

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1

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1

6

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52

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1

0

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1

-

1

-

1

-

1

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1

0

0

-

1

0

-

1

47

-

1

13

-

1

61

-

1

84

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1

55

-

1

78

-

1

41

X

-

1

-

1

-

1

-

1

-

1

-

1

0

,

wherein “−1” indicates a zero matrix having a z max ×z max size,

wherein “0” indicates an identity matrix having the z max ×z max size,

wherein a positive integer indicates a first permutation matrix having the z max ×z max size that is generated by circular shifting the identity matrix by the positive integer, and

wherein “X” is an integer from 0 to 95 and

a decoder for decoding the encoded data using the parity check matrix.

9. The apparatus of claim 8 , wherein the decoder comprises:

a memory module for storing the first base matrix;

a base matrix generation module for generating a second base matrix by replacing each first value corresponding to each element of the first base matrix with a second value corresponding to each element of the second base matrix, the second value an integer that indicates either a zero matrix or a second permutation matrix having a z×z size, wherein z is smaller than z max ;

a parity check matrix generation module for generating the parity check matrix by replacing each second value of the second base matrix with a corresponding second permutation matrix or the zero matrix having the z×z size; and

a decoding module for decoding the encoded data using the parity check matrix.

10. The apparatus of claim 9 , wherein:

the second value is either a non-negative integer or “−1;” and

the parity check matrix generation module comprises:

means for replacing each second value of “−1” with the zero matrix having the z×z size;

means for replacing each second value of a positive integer with a second permutation matrix having the z×z size, the second permutation matrix altered from an identity matrix having the z×z size according to the positive integer; and

means for replacing each second value of a zero with a second permutation matrix that is the identity matrix having the z×z size.

11. The apparatus of claim 10 , wherein the second permutation matrix indicated is altered by circular shifting either each entire row or each entire column of the identity matrix a number of intervals equal to the positive integer.

12. The apparatus of claim 9 , wherein each of the first and second permutation matrixes is defined as having a row weight and column weight of “1.”

13. The apparatus of claim 9 , wherein each second value is determined based on the following equation:

shift( z )=floor(shift( z max ) z/z max ),

wherein “shift (z max )” is the first value,

wherein “shift(z)” is the second value, and

wherein “floor (x)” denotes a nearest integer from x toward negative infinity.

14. The apparatus of claim 8 , wherein “X” is 95.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2012
From: OH, MIN SEOK; CHUNG, KYU HYUK; CHO, KI HYOUNG
To: LG ELECTRONICS INC.
Reel/Frame 028047/0040 →
Priority Claims (13)
KR 10-2004-47898 · Jun 24, 2004 · national
KR 10-2004-48454 · Jun 25, 2004 · national
KR 10-2004-85512 · Oct 25, 2004 · national
KR 10-2004-87361 · Oct 29, 2004 · national
KR 10-2004-87938 · Nov 1, 2004 · national
KR 10-2004-88807 · Nov 3, 2004 · national
KR 10-2004-109624 · Dec 21, 2004 · national
KR 10-2004-110678 · Dec 22, 2004 · national
KR 10-2004-111525 · Dec 23, 2004 · national
KR 10-2004-117136 · Dec 30, 2004 · national
KR 10-2005-00046 · Jan 3, 2005 · national
KR 10-2005-00244 · Jan 3, 2005 · national
KR 10-2005-03296 · Jan 13, 2005 · national
Continuity (3)
Continuation 12414600 · Mar 30, 2009
Continuation 11166476 · Jun 23, 2005
Related Publication 20120185746A1 · Jul 19, 2012