CMOS structure with multiple spacers
View Patent ↗A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
1. A semiconductor device comprising:
a substrate having shallow trench isolation regions and source/drain regions therein;
a gate stack overlying the substrate between the source/drain regions;
a first spacer with a first dielectric constant overlying a sidewall of the gate stack, wherein the first spacer has an exterior sidewall; and
a second spacer with a second dielectric constant overlying the exterior sidewall of the first spacer, wherein the first dielectric constant is less than the second dielectric constant, and wherein the first spacer has a first amount of a first impurity therein and the second spacer has a second amount of a second impurity therein, wherein the first amount is different from the second amount.
2. The semiconductor device of claim 1 , further comprising a liner between the gate stack and the first spacer.
3. The semiconductor device of claim 2 , wherein the liner is silicon oxide.
4. The semiconductor device of claim 1 , wherein the first dielectric constant is ranged between about 4.5 to about 5.5.
5. The semiconductor device of claim 1 , wherein the first spacer is at least one of silicon nitride, oxynitride or silicon carbide.
6. The semiconductor device of claim 1 , wherein the second spacer is at least one of silicon nitride, oxynitride or silicon carbide.
7. The semiconductor device of claim 1 , wherein the second amount is less than the first amount.
8. The semiconductor device of claim 1 , wherein the first impurity and the second impurity are selected from the group consisting of boron, carbon, fluorine or combinations thereof.
9. The semiconductor device of claim 1 , wherein an atomic ratio of the first impurity is ranged between about 2% to about 40%.
10. The semiconductor device of claim 1 , wherein an atomic ratio of the second impurity is less than about 3%.
11. The semiconductor device of claim 1 , wherein the first spacer is boron-doped nitride and the second spacer is non-doped nitride.
12. The semiconductor device of claim 1 , wherein the first spacer has a thickness ranged between about 100 Angstroms to about 400 Angstroms.
13. The semiconductor device of claim 1 , wherein the second spacer has a thickness ranged between about 50 Angstroms to about 300 Angstroms.
14. A MOS device comprising:
a semiconductor substrate having shallow trench isolation (STI) regions therein;
a gate stack overlying the semiconductor substrate between the STI regions;
lightly doped source/drain (LDD) regions in the semiconductor substrate, wherein the LDD regions are substantially aligned respectively with the edges of the gate stack;
a boron-doped gate spacer overlying a sidewall of the gate stack; and
a protection spacer located overlying an exterior sidewall of the boron-doped spacer, wherein the protection spacer compass the boron-doped gate spacer.
15. The MOS device of claim 14 , further comprising an oxide liner between the gate stack and the boron-doped gate spacer.
16. The MOS device of claim 14 , wherein the boron-doped gate spacer has a dielectric constant ranged between about 4.5 to about 5.5.
17. The MOS device of claim 14 , wherein the boron-doped gate spacer is boron-doped nitride.
18. The MOS device of claim 14 , wherein the protection spacer is non-doped nitride.
19. The MOS device of claim 14 , wherein the dielectric constant of the boron-doped gate spacer is less than the dielectric constant of the protection spacer.
20. A MOS device comprising:
a semiconductor substrate having shallow trench isolation (STI) regions therein;
a gate stack located on the semiconductor substrate between the STI regions;
lightly doped source/drain (LDD) regions in the semiconductor substrate, wherein the LDD regions are substantially aligned respectively with the edges of the gate stack;
oxide liners located on sidewalls of the gate stack;
boron-doped dielectric spacers located on exterior sidewalls of the oxide liners;
non-doped dielectric spacers located on exterior sidewalls of the boron-doped dielectric spacers, wherein the non-doped dielectric spacers compass the boron-doped dielectric spacers respectively; and
source/drain regions in the semiconductor substrate and substantially aligned respectively with the edges of the non-doped dielectric spacers.