Peak or zero current comparator
The present invention relates to a simple and small-sized circuit configuration ( 10 ) for significantly reducing resettling time of a peak or zero current comparator. This circuit configuration ( 10 ) provides the comparator input stage with an alternative current path at the comparator input submitted to a large voltage variation able to disturb the DC-settings. This circuit configuration ( 10 ) comprises a pair of small transistors (P 3 , P 4 ) coupled to a differential pair of transistors (N 1 , N 2 ) of the comparator input stage and having a polarity different from said pair of transistors (P 3 , P 4 ). The gates of the transistors P 3 and P 4 share a common terminal connected to said comparator input. The currents and voltages across the comparator are always maintained close to the normal DC-setting values during the voltage transition phase. This circuit configuration ( 10 ) can be used in any current comparator for detecting a peak or a zero current, in particular, in DC-DC converters based on a switched operating mode.
1. A circuit configuration for reducing resettling time of a current detector means, said circuit configuration comprising: a differential pair of transistors including a first transistor which is coupled between a second node and a third node, wherein said first transistor receives a first input signal of a predetermined value at a first node, and a second transistor which is coupled between said third node and a fifth node, wherein said second transistor receives a second input signal of a variable value at a fourth node, said variable value being able to make a large shift relative to said predetermined value; a pair of transistors with a polarity different from said differential pair of transistors, including a third transistor which is coupled between said second node and said third node, and a fourth transistor which is coupled between said third node and said fifth node, wherein said third transistor and said fourth transistor share a common input terminal which is connected to said fourth node.
2. The circuit configuration according to claim 1 , wherein said pair of transistors is a pair of relatively small-sized transistors.
3. The circuit configuration according to claim 1 , wherein said transistors are metal oxide semiconductor field effect transistors or bipolar junction transistors.
4. The circuit configuration according to claim 3 , wherein said variable value turns off said second transistor and turns on said fourth transistor or inversely.
5. The circuit configuration according to claim 4 , wherein said variable value and said predetermined value are provided by a DC-DC converter means based on a switched operating mode, said DC-DC converter means being a step-up DC-DC converter or a step-down DC-DC converter or any combination of such DC-DC converters.
6. A comparator input stage for setting DC-setting values and reducing resettling time, said comparator input stage comprising at least: a circuit configuration according to claim 1 ; a first load which is coupled to said second node; a second load which is coupled to said fifth node; a current source which is coupled to said third node.
7. A comparator means for measuring a peak or zero current, said comparator means comprising at least: an input stage according to claim 6 ; an output stage for outputting a signal to a driver means, said driver means controlling an ON-OFF switching sequence; optionally, a cascode stage or a folded cascode stage being located between said input stage and said output stage for reducing the Miller capacitance effect.
8. A detector means for detecting a peak or zero current, said detector means comprising at least a comparator means according to claim 7 .