IP Library › Granted Patent US 8,306,070
Granted Patent B2
US 8,306,070 · App. 11/491,628 · Granted Nov 6, 2012

Method and system for speed negotiation for twisted pair links using intelligent E-FIFO in fibre channel systems

Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 8,306,070
App. No.
11/491,628
Granted
Nov 6, 2012
Kind
B2
Abstract

Certain aspects of a method and system for speed negotiation for twisted pair links using intelligent elastic first-in-first-out (E-FIFO) in fiber channel systems are disclosed. Aspects of a method may include determination of a priority level based on amount of data in at least one elastic FIFO (E-FIFO) buffer communicatively coupled to at least one of the fiber channel host devices. The E-FIFO buffer may be modified either by insertion or deletion of IDLE words or words from an order set based on the determined priority level. The data may be synchronously communicated between fiber channel host devices communicatively coupled via the twisted pair link based on the modified elastic buffer.

Claims (32)

1. In a fibre channel system comprising fibre channel host devices communicatively coupled via a twisted pair link, a method for handling data in a communication system, the method comprising:

determining a priority level based on amount of data in at least one elastic buffer communicatively coupled to at least one fibre channel host device;

modifying said at least one elastic buffer based on said determined priority level; and

communicating data synchronously between said fibre channel host devices communicatively coupled via said twisted pair link based on said modified elastic buffer, wherein a physical (PHY) layer block of one of said fibre channel host devices operates in a master mode, wherein another PHY layer block of another of said fibre channel host devices operates in a slave mode, wherein an elastic buffer corresponding to said master PHY layer block operates according to a reference clock, and wherein another elastic buffer corresponding to said slave PHY layer block operates according to a recovered clock.

2. The method according to claim 1 , comprising modifying said at least one elastic buffer if said determined priority level indicates that said elastic buffer is empty by inserting an IDLE word and at least one word from an order set comprising: ARB(ff), ARB(fb) for blocking ARB, ARB(src_alpha) for address assignment, no operating system (NOS), offline state (OLS), link reset (LR), link reset response (LRR), loop initialization primitive (LIP), loop port bypass (LPB), and loop port enable (LPE).

3. The method according to claim 1 , comprising modifying said at least one elastic buffer if said determined priority level indicates that said elastic buffer is empty by inserting at least one current fill word after any fill word in said elastic buffer.

4. The method according to claim 1 , wherein said at least one elastic buffer is an elastic first-in first-out (FIFO) buffer.

5. The method according to claim 1 , comprising modifying said at least one elastic buffer if said determined priority level indicates a low priority deletion operation by deleting a next fill word if at least four fill words are inserted with no intervening data words.

6. The method according to claim 5 , comprising if said determined priority level indicates said low priority deletion operation and if a current fill word changes to IDLE while a deletion operation is pending, not deleting a first IDLE word.

7. The method according to claim 5 , comprising one or both of: re-entering said determined priority level that indicates said low priority deletion operation after waiting for at least four fill words before another deletion operation and entering said determined priority level that indicates a quiescent operation with no deletion operation pending.

8. The method according to claim 5 , comprising modifying said at least one elastic buffer if said determined priority level indicates a high priority deletion operation by deleting a next fill word if at least two fill words are inserted with no intervening data words.

9. The method according to claim 5 , comprising if said determined priority level indicates said high priority deletion operation and if a current fill word changes to IDLE while a deletion operation is pending, not deleting a first IDLE word.

10. The method according to claim 5 , comprising one or both of: entering said determined priority level that indicates said low priority deletion operation and waiting for at least four fill words before another deletion operation and re-entering said determined priority level that indicates a high priority deletion operation and waiting for at least two fill words before another deletion operation.

11. The method according to claim 1 , comprising operating an input pointer to said at least one elastic buffer from said reference clock and operating an output pointer to said at least one elastic buffer from said recovered clock.

12. A system for handling data in a fibre channel system comprising fibre channel host devices communicatively coupled via a twisted pair link, the system comprising:

one or more circuits that is operable to determine a priority level based on amount of data in at least one elastic buffer communicatively coupled to at least one fibre channel host device;

said one or more circuits is operable to modify said at least one elastic buffer based on said determined priority level; and

said one or more circuits is operable to communicate data synchronously between said fibre channel host devices communicatively coupled via said twisted pair link based on said modified elastic buffer, wherein a physical (PHY) layer block of one of said fibre channel host devices operates in a master mode, wherein another PHY layer block of another of said fibre channel host devices operates in a slave mode, wherein an elastic buffer corresponding to said master PHY layer block operates according to a reference clock, and wherein another elastic buffer corresponding to said slave PHY layer block operates according to a recovered clock.

13. The system according to claim 12 , wherein said one or more circuits is operable to insert an IDLE word and at least one word from an order set comprising: ARB(ff), ARB(fb) for blocking ARB, ARB(src_alpha) for address assignment, no operating system (NOS), offline state (OLS), link reset (LR), link reset response (LRR), loop initialization primitive (LIP), loop port bypass (LPB), and loop port enable (LPE), if said determined priority level indicates that said at least one elastic buffer is empty.

14. The system according to claim 12 , wherein said one or more circuits is operable to insert at least one current fill word after any fill word in said elastic buffer, if said determined priority level indicates that said at least one elastic buffer is empty.

15. The system according to claim 12 , wherein said at least one elastic buffer is an elastic first-in first-out (FIFO) buffer.

16. The system according to claim 12 , wherein said one or more circuits is operable to delete a next fill word in said at least one elastic buffer if at least four fill words are inserted with no intervening data words, and if said determined priority level indicates a low priority deletion operation.

17. The system according to claim 16 , wherein said one or more circuits is operable to disable deletion of a first IDLE word if said determined priority level indicates said low priority deletion operation, and if a current fill word changes to IDLE while a deletion operation is pending.

18. The system according to claim 16 , wherein said one or more circuits is operable to enable one or both of: re-entering said determined priority level that indicates said low priority deletion operation after waiting for at least four fill words before another deletion operation, and entering said determined priority level that indicates a quiescent operation with no deletion operation pending.

19. The system according to claim 16 , wherein said one or more circuits is operable to delete a next fill word if at least two fill words are inserted with no intervening data words, and if said determined priority level indicates a high priority deletion operation.

20. The system according to claim 16 , wherein said one or more circuits is operable to disable deletion of a first IDLE word if said determined priority level indicates said high priority deletion operation and if a current fill word changes to IDLE while a deletion operation is pending.

21. The system according to claim 16 , wherein said one or more circuits is operable to enable one or both of: entering said determined priority level that indicates said low priority deletion operation and waiting for at least four fill words before another deletion operation, and re-entering said determined priority level that indicates a high priority deletion operation and waiting for at least two fill words before another deletion operation.

22. The system according to claim 12 , wherein said one or more circuits enables operation of an input pointer to said at least one elastic buffer from said reference clock and operating an output pointer to said at least one elastic buffer from said recovered clock.

23. A method implemented in a fibre channel system comprising fibre channel host devices communicatively coupled via a twisted pair link, the method comprising:

determining a priority level based on an amount of data in an elastic buffer coupled to one of the fibre channel host devices for facilitating speed negotiation between the fibre channel host devices over the twisted pair link, wherein the priority level corresponds to performing one of: a deletion operation, an insertion operation, and a quiescent operation;

modifying the elastic buffer based on the determined priority level;

communicating data synchronously between the fibre channel host devices based on the modified elastic buffer, wherein a physical (PHY) layer block of one of the fibre channel host devices operates in a master mode, wherein another PHY layer block of another of the fibre channel host devices operates in a slave mode, wherein an elastic buffer corresponding to the master PHY layer block operates according to a reference clock, and wherein another elastic buffer corresponding to the slave PHY layer block operates according to a recovered clock.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2006
From: GHIASI, ALI
To: BROADCOM CORPORATION
Reel/Frame 018392/0626 →
Continuity (2)
Provisional Application 60742196 · Dec 2, 2005
Related Publication 20070133562A1 · Jun 14, 2007