System and method for branch misprediction prediction using a mispredicted branch table having entry eviction protection

1. A hardware system for providing branch misprediction prediction in a microprocessor, said system comprising:

a mispredicted branch table that includes address, distance, and true/not true fields; and

an index to the mispredicted branch table that is formed responsive to 1) a current mispredicted branch, 2) a global history, 3) a global misprediction history, and 4) a branch misprediction distance, wherein a plurality of incorrect predictions are required to evict a mispredicted branch table entry to protect the mispredicted branch table entry from being evicted based on a single misprediction or aliasing event only.

2. The system as claimed in claim 1 , wherein said system further includes a misprediction distance register that is in communication with the mispredicted branch table.

3. The system as claimed in claim 1 , wherein said system further includes a concatenated register of global history bits and global misprediction history bits.

4. The system as claimed in claim 1 , wherein said system further includes a branch counter that is employed to track a number of correctly predicted branches between mispredictions.

5. The system as claimed in claim 1 , wherein said system operates outside of a functional path of a branch predictor.

6. The system as claimed in claim 1 , wherein said system predicts which future branch will be mispredicted next and predicts a misprediction time when the future branch is mispredicted will occur.

7. The system as claimed in claim 6 , wherein said system further changes a prediction of the future branch that will be mispredicted next at the misprediction time.

8. The system as claimed in claim 1 , wherein said system counts a distance, in committed branches, between consecutive branch mispredictions.

9. The system as claimed in claim 8 , wherein said distance, in committed branches, between consecutive branch mispredictions, represents a time prediction of when a next branch misprediction will occur.

10. The system as claimed in claim 1 , wherein said mispredicted branch table further includes a used data field that is indicative of whether an associated prediction was incorrect.

11. The method as claimed in claim 1 , wherein said plurality of incorrect predictions comprises a first incorrect prediction that clears a used bit but does not clear a distance estimator register, a mispredicted program counter, or the true/not true fields, and a second incorrect prediction that evicts the mispredicted branch table entry.

12. A system for providing branch misprediction prediction in a microprocessor, said system comprising:

a mispredicted branch table that includes address and distance data regarding mispredictions;

a distance estimator register and a history register that are coupled to the mispredicted branch table for providing the address and distance data to the table regarding a future branch that is expected to be mispredicted and misprediction time that the future branch is expected to be mispredicted; and

an index to the mispredicted branch table that is employed to predict branch mispredictions, wherein a plurality of incorrect predictions are required to evict a mispredicted branch table entry to protect the mispredicted branch table entry from being evicted based on a single misprediction or aliasing event only.

13. The system as claimed in claim 12 , wherein said history register includes a concatenated register of global history bits and global misprediction history bits.

14. The system as claimed in claim 12 , wherein said mispredicted branch table further includes true/not true fields.

15. The system as claimed in claim 12 , wherein said system counts a distance, in committed branches, between consecutive branch mispredictions.

16. The system as claimed in claim 12 , wherein said system interacts with a branch predictor only for branches that are predicted to be mispredicted or have actually been mispredicted.

17. The system as claimed in claim 12 , wherein said system operates outside of a function path of a branch predictor.

18. The system as claimed in claim 12 , wherein said plurality of incorrect predictions comprises a first incorrect prediction that clears a used bit but does not clear the distance estimator register, a mispredicted program counter, or true/not true fields, and a second incorrect prediction that evicts the mispredicted branch table entry.

19. A method of predicting branch mispredictions in a microprocessor, said method comprising the steps of:

providing misprediction address and distance data to a mispredicted branch table from a history register and a distance estimator; and

accessing the mispredicted branch table outside of a function path of a branch predictor to predict branch misprediction, wherein a plurality of incorrect predictions are required to evict a mispredicted branch table entry to protect the mispredicted branch table entry from being evicted based on a single misprediction or aliasing event only.

20. The method as claimed in claim 19 , wherein said method further includes the step of counting a distance, in committed branches, between consecutive branch mispredictions.

21. The method as claimed in claim 19 , wherein said misprediction branch table further includes true/not true data.

22. The method as claimed in claim 19 , wherein said step of providing misprediction address and distance data to the mispredicted branch table further includes performing at least one exclusive OR operation.

23. The method as claimed in claim 19 , wherein said plurality of incorrect predictions comprises a first incorrect prediction that clears a used bit but does not clear a distance estimator register, a mispredicted program counter, or true/not true fields, and a second incorrect prediction that evicts the mispredicted branch table entry.