IP Library › Granted Patent US 8,314,658
Granted Patent B2
US 8,314,658 · App. 12/882,592 · Granted Nov 20, 2012

Power amplifier

Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,314,658
App. No.
12/882,592
Granted
Nov 20, 2012
Kind
B2
Abstract

A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.

Claims (32)

1. A power amplifier comprising:

a plurality of primary inductors arranged as a whole in a circular geometry over a semiconductor substrate; and

a plurality of amplifier pairs provided corresponding to the primary inductors on the semiconductor substrate, respectively, each amplifier pair including first and second amplifiers coupled, respectively, to two ends of a corresponding primary inductor, each of said first and second amplifiers having an input node coupled, respectively, to a common first input terminal and a common second input terminal, and amplifying and outputting to the corresponding primary inductor each of a pair of first and second signals given as differential input signals,

a secondary inductor provided adjacent to the primary inductors over the semiconductor substrate and arranged in a circular geometry with one turn or multiple turns and, by being magnetically coupled to the primary inductors, further combining and outputting signals made by combining the first and second signals at each of the primary inductors; and

a connection wiring provided inside the primary inductors over the semiconductor substrate and electrically coupling middle points of the primary inductors with each other,

wherein each of the middle points is a point over the primary inductor and also a point at the same distances from two ends of the primary inductor and

wherein said plurality of primary inductors and said connection wiring are formed using same wiring layer.

2. A power amplifier according to claim 1 ,

wherein an overall shape of the inductors is formed so as to be rotationally symmetrical about a particular central axis which is perpendicular to the semiconductor substrate and to be mirror symmetrical relative to each of a particular plurality of symmetrical planes containing the central axis,

wherein the middle point of each of the primary inductors is contained in one of the symmetrical planes,

wherein the connection wiring comprises a plurality of wiring parts corresponding to the primary inductors, respectively, and

wherein each of the wiring parts couples a central point, which is an intersection point of the central axis and the semiconductor substrate surface, with a middle point of the corresponding primary inductor, and is provided along a symmetrical plane passing through the middle point of the corresponding primary inductor.

3. A power amplifier according to claim 2 ,

wherein the secondary inductor is a multiple turn inductor including one crossing part or a plurality of crossing parts, and

wherein the one crossing part or each of the crossing parts is provided close to one of the symmetrical planes.

4. A power amplifier according to claim 2 ,

wherein each of the first and second amplifiers has transistors operated by a drive voltage,

wherein the drive voltage is supplied from an external device to a middle point of a first primary inductor which is one of the primary inductors,

wherein the drive voltage is supplied to the transistors coupled to two ends of the first primary inductor through the first primary inductor, and

wherein the drive voltage is supplied to the transistors coupled to two ends of a second primary inductor being different from the first primary inductor of the primary inductors through the connection wiring and the second primary inductor.

5. A power amplifier according to claim 2 ,

wherein each of the first and second amplifiers has transistors operated by a drive voltage,

wherein the drive voltage is supplied from an external device to the central point over the connection wiring, and

wherein the drive voltage is supplied to the transistors coupled to two ends of a first primary inductor of the primary inductors through the connection wiring and the first primary inductor.

6. A power amplifier according to claim 2 ,

wherein each of the first and second amplifiers has transistors operated by a drive voltage,

wherein the drive voltage is supplied from an external device to a middle point of each of the primary inductors, and

wherein the drive voltage is supplied to the transistors coupled to two ends of a first primary inductor of the primary inductors through the first primary inductor.

7. A power amplifier according to claim 6 , further comprising a plurality of bypass capacitors coupled individually between the middle point of the respective primary inductors and a ground node.

8. A power amplifier according to claim 2 , wherein the first and second amplifiers coupled to each of the primary inductors are arranged as a whole to be mirror symmetrical relative to each of the symmetrical planes.

9. A power amplifier according to claim 8 , further comprising, with respect to each of the primary inductors, first and second signal lines for supplying the first and second signals to the first and second amplifiers,

wherein the first and second signal lines are provided at a position mirror symmetrical to a symmetrical plane passing through a middle point of a corresponding primary inductor.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2010
From: KAWAKAMI, TSUYOSHI; FURUKAWA, AKIHIKO; YAMAKAWA, SATOSHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024992/0058 →
Priority Claims (1)
JP 2009-214308 · Sep 16, 2009 · national
Continuity (1)
Related Publication 20110063028A1 · Mar 17, 2011