SOVA sharing during LDPC global iteration

1. A system for decoding information, comprising:

a processor; and

a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to:

decode analog to digital converted (ADC) data using a Viterbi decoder;

decode an output of an iterative error correction decoder using the Viterbi decoder in the event error correction decoding by the iterative error correction decoder fails;

decode Viterbi decoded data generated by the Viterbi decoder using the iterative error correction decoder; and

send, from the iterative error correction decoder to a memory, a reservation request prior to completion of the decoding of the Viterbi decoded data by the iterative error correction decoder.

2. The system of claim 1 , wherein the memory is further configured to provide the processor with instructions which when executed cause the processor to store, in a second memory, the ADC data and to pass the ADC data from the second memory to the Viterbi decoder.

3. The system of claim 1 , wherein the iterative error correction decoder includes a low-density parity-check (LDPC) decoder.

4. The system of claim 1 , wherein the Viterbi decoder includes a soft output Viterbi decoder.

5. The system of claim 1 , wherein:

in the event error correction decoding fails and a number of failures for that sector exceeds a maximum number of failures, the iterative error correction decoder is configured to declare a failure; and

in the event error correction decoding fails and the number of failures for that sector does not exceed the maximum number of failures, the iterative error correction decoder is configured to retry the sector by passing the output of the iterative error correction decoder to the Viterbi decoder for decoding.

6. The system of claim 1 , wherein the memory is further configured to provide the processor with instructions which when executed cause the processor to store data output by the Viterbi decoder in the event the iterative error correction decoder is occupied.

7. The system of claim 1 , wherein the system is used in place of another system that includes two or more soft output Viterbi decoders.

8. The system of claim 1 , wherein the system includes one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

9. The system of claim 1 , wherein the memory is further configured to provide the processor with instructions which when executed cause the processor to send, from the iterative error correction decoder to the memory, a reservation cancellation in the event error correction decoding of the Viterbi decoded data by the iterative error correction decoder succeeds.

10. The system of claim 9 , wherein the memory is further configured to provide the processor with instructions which when executed cause the processor to send, from the iterative error correction decoder to the memory, extrinsic information associated with the reservation request in the event error correction decoding of the Viterbi decoded data by the iterative error correction decoder fails.

11. A method for decoding information, comprising:

decoding analog to digital converted (ADC) data using a Viterbi decoder;

decoding an output of an iterative error correction decoder using the Viterbi decoder in the event error correction decoding by the iterative error correction decoder fails;

decoding Viterbi decoded data generated by the Viterbi decoder using the iterative error correction decoder; and

sending, from the iterative error correction decoder to a memory, a reservation request prior to completion of the decoding of the Viterbi decoded data by the iterative error correction decoder.

12. The method of claim 11 further comprising storing, in a second memory, the ADC data and passing the ADC data from the second memory to the Viterbi decoder.

13. The method of claim 11 , wherein the iterative error correction decoder includes a low-density parity-check (LDPC) decoder.

14. The method of claim 11 , wherein the Viterbi decoder includes a soft output Viterbi decoder.

15. The method of claim 11 , wherein:

in the event error correction decoding fails and a number of failures for that sector exceeds a maximum number of failures, the iterative error correction decoder is configured to declare a failure; and

in the event error correction decoding fails and the number of failures for that sector does not exceed the maximum number of failures, the iterative error correction decoder is configured to retry the sector by passing the output of the iterative error correction decoder to the Viterbi decoder for decoding.

16. The method of claim 11 further comprising storing data output by the Viterbi decoder in the event the iterative error correction decoder is occupied.

17. The method of claim 11 , wherein the method is performed using one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

18. The method of claim 11 further comprising sending, from the iterative error correction decoder to the memory, a reservation cancellation in the event error correction decoding of the Viterbi decoded data by the iterative error correction decoder succeeds.

19. The method of claim 18 further comprising sending, from the iterative error correction decoder to the memory, extrinsic information associated with the reservation request in the event error correction decoding of the Viterbi decoded data by the iterative error correction decoder fails.

20. A computer program product for decoding information, the computer program product being embodied in a tangible computer readable storage medium and comprising computer instructions for:

decoding analog to digital converted (ADC) data using a Viterbi decoder;

decoding an output of an iterative error correction decoder using the Viterbi decoder in the event error correction decoding by the iterative error correction decoder fails;

decoding Viterbi decoded data generated by the Viterbi decoder using the iterative error correction decoder; and

sending, from the iterative error correction decoder to a memory, a reservation request prior to completion of the decoding of the Viterbi decoded data by the iterative error correction decoder.

21. The computer program product of claim 20 further comprising computer instructions for sending, from the iterative error correction decoder to the memory, a reservation cancellation in the event error correction decoding of the Viterbi decoded data by the iterative error correction decoder succeeds.

22. The computer program product of claim 21 further comprising computer instructions for sending, from the iterative error correction decoder to the memory, extrinsic information associated with the reservation request in the event error correction decoding of the Viterbi decoded data by the iterative error correction decoder fails.