IP Library Granted Patent US 8,324,622
Granted Patent B2
US 8,324,622 · App. 12/651,332 · Granted Dec 4, 2012

Method of repairing probe pads

Assignees: STMicroelectronics Inc.; International Business Machines Corporation
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Quick Facts
Patent No.
US 8,324,622
App. No.
12/651,332
Granted
Dec 4, 2012
Kind
B2
Abstract

A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Claims (33)

1. A device, comprising:

a substrate;

a first level of active circuitry formed on the substrate;

a first metal level coupled to the first level of active circuitry, the first metal level including:

a first probe pad having a first surface planarized by a first chemical mechanical polish, the first probe pad having a first indentation;

a portion of a first insulating layer in the first indentation, the first insulating layer having a second surface that is coplanar with the first surface of the first probe pad, the first indentation being partially filled by the portion of the first insulating layer; and

a second metal level coupled to the first metal level, the second metal level including:

a second probe pad having a third surface planarized by a second chemical mechanical polish.

2. The device of claim 1 wherein the first probe pad is formed overlying the first level of active circuitry.

3. The device of claim 1 wherein the second probe pad is formed overlying the first probe pad.

4. The device of claim 1 wherein the second probe pad is formed overlying the first level of active circuitry.

5. The device of claim 1 , further comprising a second insulating layer formed between the first metal level and the second metal level, a portion of the second insulating layer filling a remainder of the first indentation.

6. The device of claim 1 , further comprising a second indentation in the second probe pad.

7. The device of claim 6 , wherein the second indentation in the second probe pad is partially filled by a second insulating layer.

8. A device, comprising:

a substrate;

an integrated circuit formed on the substrate;

a first metal layer coupled to the integrated circuit, the first metal layer having a first surface, the first metal layer including:

a probe pad having the first surface, the probe pad including an indentation that extends below the first surface;

a first insulating layer on the first metal layer and including a first portion positioned in the indentation of the probe pad;

a second insulating layer, the indentation including the second insulating layer adjacent to the first portion of the first insulating layer, the second insulating layer having a second surface that is coplanar with the first surface; and

a second metal layer on the first insulating layer.

9. The device of claim 8 , further comprising a third insulating layer on the first metal layer, the third insulating layer having a third surface that is coplanar with a fourth surface of the second metal layer.

10. The device of claim 9 wherein the second metal layer includes a second probe pad.

11. The device of claim 10 wherein the second probe pad has a fourth surface positioned above the first surface.

12. A device, comprising:

a substrate;

an integrated circuit formed on the substrate;

a first metal layer coupled to the integrated circuit, the first metal layer having a first surface, the first metal layer including:

a probe pad having the first surface, the probe pad including an indentation that extends below the first surface;

a first insulating layer on the first metal layer and including a first portion positioned in the indentation of the probe pad;

a second insulating layer adjacent to the first metal layer, the second insulating layer having a second surface that is coplanar with the first surface; and

a second metal layer on the first insulating layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2013
From: ECONOMIKOS, LAERTIS; NIEUWENHUIZEN, ROBIN VAN DEN; TSENG, WEI-TSU
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 029933/0721 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2013
From: ZHANG, JOHN H.
To: STMICROELECTRONICS, INC.
Reel/Frame 029933/0757 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2010
From: ZHANG, JOHN H.; ECONOMIKOS, LAERTIS; NIEUWENHUIZEN, ROBIN VAN DEN; TSENG, WEI-TSU
To: STMICROELECTRONICS, INC.; IBM SEMICONDUCTOR RESEARCH AND DEVELOPMENT CENTER (SRDC)
Reel/Frame 024118/0343 →
Continuity (1)
Related Publication 20110156032A1 · Jun 30, 2011