IP Library Granted Patent US 8,325,793
Granted Patent B2
US 8,325,793 · App. 12/435,538 · Granted Dec 4, 2012

Precursor ISI cancellation using adaptation of negative gain linear equalizer

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,325,793
App. No.
12/435,538
Granted
Dec 4, 2012
Kind
B2
Abstract

An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate an equalized signal in response to an input signal and an equalizer parameter signal. The equalizer parameter signal generally causes a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in the input signal. The second circuit may be configured to generate (i) the equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to the equalized signal. The control signal generally causes an adjustment of the equalizer parameter signal. The adjustment of the equalizer parameter signal generally causes a decrease in the pre-cursor inter-symbol interference from the symbols.

Claims (29)

1. An apparatus comprising:

a first circuit comprising a negative gain linear equalizer circuit, said first circuit configured to generate an equalized signal in response to an input signal and an equalizer parameter signal, said equalizer parameter signal causing a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in said input signal; and

a second circuit configured to generate (i) said equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to said equalized signal, said control signal causing an adjustment of said equalizer parameter signal, said adjustment of said equalizer parameter signal causing a decrease in said pre-cursor inter-symbol interference from said symbols.

2. The apparatus according to claim 1 , wherein said second circuit comprises a Mueller-Muller baud-rate clock and data recovery circuit.

3. The apparatus according to claim 1 , wherein said second circuit comprises a Minimum Mean-Squared-Error baud-rate clock and data recovery circuit.

4. The apparatus according to claim 1 , wherein said second circuit further comprises an adaptive decision feedback equalizer.

5. The apparatus according to claim 4 , wherein (i) said adaptive decision feedback equalizer is further configured to generate a feedback signal in response to said data output signal and (ii) said second circuit is further configured to generate an intermediate signal by subtracting said feedback signal from said equalized signal.

6. The apparatus according to claim 5 , wherein (i) said second circuit further comprises a slicer configured to generate said output signal in response to said intermediate signal and (ii) said adjustment of said equalizer parameter signal causes sampling points to move toward a center of an eye opening at an input of said slicer.

7. An apparatus comprising:

a first circuit configured to generate an equalized signal in response to an input signal and an equalizer parameter signal, said equalizer parameter signal causing a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in said input signal; and

a second circuit configured to generate (i) said equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to said equalized signal, said control signal causing an adjustment of said equalizer parameter signal, said adjustment of said equalizer parameter signal causing a decrease in said pre-cursor inter-symbol interference from said symbols, wherein said control signal comprises a target signal amplitude and said second circuit is further configured to generate an error signal in response to said equalized signal, said data output signal and said target signal amplitude.

8. The apparatus according to claim 7 , wherein said second circuit is further configured to generate said control signal in response to said error signal.

9. The apparatus according to claim 7 , wherein said second circuit is further configured to measure a rate of change in a phase of said equalized signal as said equalizer parameter signal changes.

10. The apparatus according to claim 7 , wherein said adjustment of said equalizer parameter signal comprises adaptation of a gain of said first circuit in response to said error signal and said data output signal.

11. The apparatus according to claim 10 , wherein said adaptation of said gain of said first circuit comprises multiplying samples of said error signal and samples of said data output signal according to an equation E(k)*D(k+1), where E(k) represents a sample of the error signal at a time k and D(k+1) represents a sample of the data output signal at a time k+1.

12. An apparatus comprising:

means for generating an equalized signal using a negative gain linear equalizer circuit, wherein said equalized signal is generated in response to an input signal and an equalizer parameter signal, said equalizer parameter signal causing a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in said input signal; and

means for generating (i) said equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to said equalized signal, said control signal causing an adjustment of said equalizer parameter signal, said adjustment of said equalizer parameter signal causing a decrease in said pre-cursor inter-symbol interference from said symbols.

13. A method of symbol recovery in a receiver, comprising the steps of:

(A) generating an equalized signal in response to an input signal and an equalizer parameter signal, wherein said equalizer parameter signal causes cancellation of pre-cursor inter-symbol interference from a plurality of symbols in said input signal using a negative gain linear equalizer; and

(B) generating (i) said equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to said equalized signal, wherein said control signal causes an adjustment of said equalizer parameter signal, said adjustment of said equalizer parameter signal causing a decrease in said pre-cursor inter-symbol interference from said symbols.

14. The method according to claim 13 , further comprising performing one of Mueller-Muller baud-rate clock and data recovery and Minimum Mean-Squared-Error baud-rate clock and data recovery.

15. The method according to claim 14 , further comprising (i) generating a feedback signal in response to said data output signal using an adaptive decision feedback equalizer and (ii) generating an intermediate signal by subtracting said feedback signal from said equalized signal.

16. The method according to claim 15 ,

further comprising generating said output signal in response to said intermediate signal using a slicer, wherein said adjustment of said equalizer parameter signal causes sampling points to move toward a center of an eye opening at an input of said slicer.

17. The method according to claim 13 , further comprising generating an error signal in response to said equalized signal, said data output signal and said control signal, wherein said control signal is generated in response to said error signal.

18. The method according to claim 17 , further comprising adapting a gain of said linear equalizer in response to said error signal and said data output signal.

19. The method according to claim 18 , wherein adaptation of said gain of said linear equalizer comprises multiplying samples of said error signal and samples of said data output signal according to an equation E(k)*D(k+1), where E(k) represents a sample of the error signal at a time k and D(k+1) represents a sample of the data output signal at a time k+1.

20. The apparatus according to claim 1 , wherein said negative gain linear equalizer comprises an analog filter having a high frequency pole on an order of a data rate of said input signal.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2009
From: ZHONG, LIZHI
To: LSI CORPORATION
Reel/Frame 022638/0052 →
Continuity (1)
Related Publication 20100284686A1 · Nov 11, 2010