Thin film transistor with a plurality of oxide clusters over the gate insulating layer
View Patent ↗In a thin film transistor including an oxide semiconductor, an oxide cluster having higher electrical conductance than the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer, whereby field effect mobility of the thin film transistor can be increased and increase of off current can be suppressed.
1. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a plurality of oxide clusters over the gate insulating layer;
an oxide semiconductor layer over the gate insulating layer; and
source and drain electrode layers over the oxide semiconductor layer,
wherein the plurality of oxide clusters have electrical conductivity,
wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other,
wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other, and
wherein a channel formation region is formed in the oxide semiconductor layer and the plurality of oxide clusters.
2. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes at least one of indium, gallium, and zinc.
3. The semiconductor device according to claim 1 , wherein the plurality of oxide clusters includes at least one of indium, zinc, tin, molybdenum, and tungsten.
4. The semiconductor device according to claim 1 , wherein the plurality of oxide clusters includes at least one of indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, molybdenum oxide, and tungsten oxide.
5. The semiconductor device according to claim 1 , wherein electrical conductance of the plurality of oxide clusters is higher than electrical conductance of the oxide semiconductor layer.
6. The semiconductor device according to claim 1 , wherein a film thickness of the oxide semiconductor layer is equal to or greater than 30 nm and equal to or less than 100 nm.
7. The semiconductor device according to claim 1 , wherein a height of the plurality of oxide clusters from a reference surface in contact with the gate insulating layer is equal to or greater than 3 nm and equal to or less than 5 nm.
8. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer has a region which is between the source and drain electrode layers and whose thickness is smaller than a thickness of a region overlapping with the source and drain electrode layers.
9. The semiconductor device according to claim 1 , wherein a channel protective layer including an inorganic material is formed over the oxide semiconductor layer.
10. An electronic device provided with a display portion, wherein the display portion comprises the semiconductor device according to claim 1 .
11. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a plurality of oxide clusters over the gate insulating layer;
an oxide semiconductor layer over the gate insulating layer;
a buffer layer having n-type electrical conductivity over the oxide semiconductor layer; and
source and drain electrode layers over the buffer layer,
wherein the plurality of oxide clusters have electrical conductivity,
wherein a carrier concentration of the buffer layer is higher than a carrier concentration of the oxide semiconductor layer,
wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other with the buffer layer interposed therebetween,
wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other with the buffer layer interposed therebetween, and
wherein a channel formation region is formed in the oxide semiconductor layer and the plurality of oxide clusters.
12. The semiconductor device according to claim 11 , wherein the oxide semiconductor layer and the buffer layer include at least one of indium, gallium, and zinc.
13. The semiconductor device according to claim 11 , wherein the plurality of oxide clusters includes at least one of indium, zinc, tin, molybdenum, and tungsten.
14. The semiconductor device according to claim 11 , wherein the plurality of oxide clusters includes at least one of indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, molybdenum oxide, and tungsten oxide.
15. The semiconductor device according to claim 11 , wherein electrical conductance of the plurality of oxide clusters is higher than electrical conductance of the oxide semiconductor layer.
16. The semiconductor device according to claim 11 , wherein a film thickness of the oxide semiconductor layer is equal to or greater than 30 nm and equal to or less than 100 nm.
17. The semiconductor device according to claim 11 , wherein a height of the plurality of oxide clusters from a reference surface in contact with the gate insulating layer is equal to or greater than 3 nm and equal to or less than 5 nm.
18. The semiconductor device according to claim 11 , wherein the oxide semiconductor layer has a region which is between the source and drain electrode layers and whose thickness is smaller than a thickness of a region overlapping with the source and drain electrode layers.
19. The semiconductor device according to claim 11 , wherein a channel protective layer including an inorganic material is formed over the oxide semiconductor layer.
20. An electronic device provided with a display portion, wherein the display portion comprises the semiconductor device according to claim 11 .