IP Library › Granted Patent US 8,330,893
Granted Patent B2
US 8,330,893 · App. 12/447,744 · Granted Dec 11, 2012

Active matrix substrate and display device equipped with the same

Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,330,893
App. No.
12/447,744
Granted
Dec 11, 2012
Kind
B2
Abstract

An active matrix substrate ( 20 a ) defining a display region (D) which contributes to display and a frame region (F) which is arranged outside the display region (D) and does not contribute to display, the active matrix substrate ( 20 a ) comprising: a grounding wire ( 23 ) extending along a circumference of the frame region (F) in the frame region (F), wherein a gate electrode line ( 14 b ), part of which overlapping the grounding wire ( 23 ) constitutes an electrostatic protection element ( 25 ), is arranged in part of the frame region (F) outside the grounding wire ( 23 ).

Claims (21)

1. An active matrix substrate including a display region which contributes to display and a frame region which is arranged outside the display region and does not contribute to the display, the active matrix substrate comprising:

a grounding wire extending along a circumference of the frame region in the frame region,

a gate driver being located inside the grounding wire so that the gate driver is located closer to the display region than is the grounding wire,

wherein a gate electrode line, part of which overlapping the grounding wire to form at least part of an electrostatic protection element, is arranged in part of the frame region outside the grounding wire, and

wherein the gate driver is located between the display region and the grounding wire as viewed from above.

2. The active matrix substrate of claim 1 , wherein the grounding wire and the gate electrode line of the electrostatic protection element are electrically connectable through a semiconductor layer.

3. The active matrix substrate of claim 1 , wherein the grounding wire is electrically connected to a common electrode of a counter substrate arranged to face the active matrix substrate.

4. The active matrix substrate of claim 1 , wherein the grounding wire has a discharge projection projecting toward the gate electrode line.

5. The active matrix substrate of claim 1 , wherein the gate electrode line has a discharge projection projecting toward the grounding wire.

6. The active matrix substrate of claim 1 , wherein a driver circuit is arranged in part of the frame region on the side of the grounding wire close to the display region.

7. The active matrix substrate of claim 1 , wherein the part of the frame region outside the grounding wire is a buffer region which prevents the display region from being affected by corrosion and/or break.

8. A display panel comprising:

an active matrix substrate;

a counter substrate which is arranged to face the active matrix substrate and has a common electrode; and

a display layer inserted between the active matrix substrate and the counter substrate,

the display panel defining a display region which contributes to display and a frame region which is arranged outside the display region and does not contribute to display, and

the active matrix substrate including a grounding wire extending along a circumference of the frame region and electrically connected to the common electrode of the counter substrate,

wherein an electrode line, part of which overlapping the grounding wire to form part of an electrostatic protection element, is arranged in part of the frame region outside the grounding wire, wherein a majority of the electrode line is located outside the display region and outside the grounding wire, and wherein opposing end portions of the electrode line overlap the grounding wire,

a gate driver located inside the grounding wire so that the gate driver is located closer to the display region than is at least a portion of the grounding wire, and

wherein the gate driver is located between the display region and the grounding wire as viewed from above.

9. The display panel of claim 8 , wherein the electrode line is a gate electrode line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2009
From: SATOH, MASAKAZU
To: SHARP KABUSHIKI KAISHA
Reel/Frame 022613/0274 →
Priority Claims (1)
JP 2006-346523 · Dec 22, 2006 · national
Continuity (1)
Related Publication 20100073587A1 · Mar 25, 2010