Using synthesis to place macros
In one embodiment, a design methodology is described in which a functional description of each macro may be synthesized along with the other logic in a block. The resulting circuitry, including synthesized circuitry corresponding to each macro, may be placed within an area designated for the integrated circuit. The result may be analyzed, determining a location for the macro based on the location of the corresponding synthesized circuitry. For example, the geometric center of the synthesized circuitry may be located, and the geometric center of the custom circuitry associated with the macro may be placed at the same point as the geometric center of the synthesized circuitry. Because the macros are not placed in advance, the location of the macro may be controlled by other factors such as timing, space, wiring congestion, etc.
1. A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed:
invoke a synthesis tool to synthesize a plurality of blocks, wherein at least one of the blocks includes at least one macro, and wherein the macro is represented in the at least one block for the synthesis tool as a synthesizable description;
invoke a placement tool to place a result of the synthesis tool, wherein the result includes synthesized circuitry corresponding to the macro; and
analyze the placement of the synthesized circuitry to determine a location at which a predesigned circuit corresponding to the macro is to be instantiated within an integrated circuit, wherein the predesigned circuit is designed prior to synthesis of the plurality of blocks.
2. The non-transitory computer accessible storage medium as recited in claim 1 wherein the plurality of instructions, when executed, scale dimensions of the synthesized circuitry corresponding to the macro to account for an expected size increase between a size of the predetermined circuit that corresponds to the macro and a size of the synthesized circuitry prior to scaling.
3. The non-transitory computer accessible storage medium as recited in claim 2 wherein the expected size increase is about 2 to 3 times the size of the predesigned circuit, and wherein the scaling comprises scaling the dimensions by about one half to one third.
4. The non-transitory computer accessible storage medium as recited in claim 1 wherein the location is a geometric center of the synthesized circuitry subsequent to placement by the placement tool.
5. The non-transitory computer accessible storage medium as recited in claim 1 wherein the synthesis tool performs a flat synthesis in which hierarchy in the plurality of blocks is removed.
6. The non-transitory computer accessible storage medium as recited in claim 1 wherein the plurality of instructions, when executed, replace a first macro in the plurality of blocks with the synthesized circuitry responsive to analyzing the placement.
7. A computer system comprising:
a processor configured to execute instructions; and
a computer accessible storage medium coupled to the processor and storing a plurality of instructions which, when executed by the processor:
invoke a synthesis tool to synthesize a plurality of blocks, wherein at least one of the blocks includes at least one macro, and wherein the macro is represented in the at least one block for the synthesis tool as a synthesizable description;
invoke a placement tool to place a result of the synthesis tool, wherein the result includes synthesized circuitry corresponding to the macro; and
analyze the placement of the synthesized circuitry to determine a location at which a predesigned circuit corresponding to the macro is to be instantiated within an integrated circuit, wherein the predesigned circuit is designed prior to synthesis of the plurality of blocks.
8. The computer system as recited in claim 7 wherein the plurality of instructions, when executed, scale dimensions of the synthesized circuitry corresponding to the macro to account for an expected size increase between a size of the predetermined circuit that corresponds to the macro and a size of the synthesized circuitry prior to scaling.
9. The computer system as recited in claim 8 wherein the expected size increase is about 2 to 3 times the size of the predesigned circuit, and wherein the scaling comprises scaling the dimensions by about one half to one third.
10. The computer system as recited in claim 7 wherein the location is a geometric center of the synthesized circuitry subsequent to placement by the placement tool.
11. The computer system as recited in claim 7 wherein the synthesis tool performs a flat synthesis in which hierarchy in the plurality of blocks is removed.
12. The computer system as recited in claim 7 wherein the plurality of instructions, when executed, replace a first macro in the plurality of blocks with the synthesized circuitry responsive to analyzing the placement.
13. A method comprising:
a computer executing a synthesis tool to synthesize a plurality of blocks, wherein at least one of the blocks includes at least one macro, and wherein the macro is represented in the at least one block for the synthesis tool as a synthesizable description;
the computer executing a placement tool to place a result of the synthesis tool, wherein the result includes synthesized circuitry corresponding to the macro; and
analyzing the placement of the synthesized circuitry to determine a location at which a predesigned circuit corresponding to the macro is to be instantiated within an integrated circuit, wherein the predesigned circuit is designed prior to synthesizing the plurality of blocks.
14. The method as recited in claim 13 further comprising the computer scaling dimensions of the synthesized circuitry corresponding to the macro to account for an expected size increase between a size of the predetermined circuit that corresponds to the macro and a size of the synthesized circuitry prior to scaling.
15. The method as recited in claim 14 wherein the expected size increase is about 2 to 3 times the size of the predesigned circuit, and wherein the scaling comprises scaling the dimensions by about one half to one third.
16. The method as recited in claim 13 wherein the location is a geometric center of the synthesized circuitry subsequent to placement by the placement tool.
17. The method as recited in claim 13 wherein the synthesis tool performs a flat synthesis in which hierarchy in the plurality of blocks is removed.
18. The method as recited in claim 13 further comprising replacing a first macro in the plurality of blocks with the synthesized circuitry responsive to analyzing the placement.