High breakdown voltage double-gate semiconductor device
A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.
1. A method comprising:
defining a well region within a substrate with a first dopant;
defining a source region in the substrate outside of the well region, and a drain region within the substrate and within the well region, with a second dopant;
defining a first gate region within the substrate and within the well region with a third dopant;
forming a dielectric layer on the substrate between the source region and the well region;
defining a first doped region within the substrate and between the dielectric layer and the first gate region with the second dopant, the first doped region also being within the well region;
defining a second doped region within the substrate, outside of the well region, and between the dielectric layer and the first doped region with the second dopant;
forming a first electrically conductive layer on the dielectric layer; and
forming a second electrically conductive layer on the substrate and contacting both the first and second doped regions.
2. The method of claim 1 wherein the first and second dopants are the same.
3. The method of claim 1 further comprising forming control circuitry coupling between the first electrically conductive layer and the first gate region and configured to bias the first gate region as a function of a bias applied to the first electrically conductive layer.
4. The method of claim 3 wherein forming the control circuitry comprises forming a capacitor.
5. The method of claim 4 wherein forming the capacitor includes forming multiple stacked metal layers.
6. A method comprising:
providing a double-gate semiconductor device including
a substrate,
a well region defined within the substrate,
a source region defined within the substrate and outside of the well region,
a drain region defined within the substrate and within the well region,
a MOS gate disposed on the substrate between the source and drain regions and outside of the well region,
a junction gate defined within the substrate and within the well region and between the drain region and the MOS gate, and
control circuitry coupling the MOS and junction gates; and
switching between
applying a first voltage greater than a gate threshold voltage to the MOS gate while applying a second voltage to the junction gate, where the second voltage is dependent on the first voltage, and
applying a third voltage less than the gate threshold voltage to the MOS gate while applying a fourth voltage to the junction gate, where the fourth voltage is dependent on the third voltage.
7. The method of claim 6 wherein switching between applying the first voltage to the MOS gate and applying the third voltage to the MOS gate comprises applying a radio-frequency signal.
8. A method comprising:
providing a double-gate semiconductor device including
a substrate,
a well region defined within the substrate,
a source region defined within the substrate and outside of the well region,
a drain region defined within the substrate and within the well region,
a MOS gate disposed on the substrate between the source and drain regions and outside of the well region,
a junction gate, capacitively coupled to the MOS gate, and defined within the substrate and within the well region and between the drain region and the MOS gate; and
applying an RF signal to both the MOS gate and the junction gate.