Multiple seal ring structure
View Patent ↗The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures. A semiconductor device fabricated by such a method is also provided.
1. A semiconductor device, comprising:
a substrate having a seal ring region and a circuit region;
a first seal ring structure disposed over the seal ring region;
a second seal ring structure disposed over the seal ring region and adjacent to the first seal ring structure;
a third seal ring structure between the first and second seal ring structures at a corner section, the third seal ring structure having a triangular shape; and
a first passivation layer disposed over the first, second, and third seal ring structures.
2. The semiconductor device of claim 1 , wherein the first and second seal ring structures are each comprised of a stack of metal layers disposed around the circuit region.
3. The semiconductor device of claim 1 , wherein the first and second seal ring structures each have a line-shaped metal layer.
4. The semiconductor device of claim 1 , wherein the second seal ring structure is concentric to the first seal ring structure.
5. The semiconductor device of claim 1 , wherein the first seal ring structure is adjacent the circuit region and the second seal ring structure is adjacent a scribe line.
6. The semiconductor device of claim 1 , wherein the first and second seal ring structures each have a plurality of linear-shaped metal layers.
7. The semiconductor device of claim 1 , wherein the first passivation layer is comprised of silicon oxide.
8. The semiconductor device of claim 1 , further comprising a second passivation layer disposed under the first and second seal ring structures.
9. A semiconductor device, comprising:
a substrate having a seal ring region and a circuit region;
a first seal ring structure disposed over the seal ring region adjacent the circuit region, the first seal ring structure having a plurality of linear-shaped metal layers;
a second seal ring structure disposed over the seal ring region adjacent to a scribe line and the first seal ring structure, the second seal ring structure having a plurality of linear-shaped metal layers;
a third seal ring structure disposed over the seal ring region and between the first and second seal ring structures at a corner section, the third seal ring structure having a plurality of triangular-shaped metal layers; and
a first passivation layer disposed over the first, second, and third seal ring structures.
10. The semiconductor device of claim 9 , wherein the first, second, and third seal ring structures are each comprised of a stack of metal layers disposed around the circuit region.
11. The semiconductor device of claim 9 , wherein the second and third seal ring structures have line-shaped legs running in parallel to each other.
12. The semiconductor device of claim 9 , wherein the second seal ring structure is concentric to the first seal ring structure.
13. The semiconductor device of claim 9 , wherein the first passivation layer is comprised of silicon oxide.
14. The semiconductor device of claim 9 , further comprising a second passivation layer disposed under the first and second seal ring structures.